2
\$\begingroup\$

Lets say we have this circuit:

enter image description here

tpd(AND)=5 ns, tpd(OR)=5ns, tpd(NOT)=3ns, and tcd of all gates =1ns

FlipFlops: tpcq=1ns, tccq=1ns, tsetup=1ns thold=1ns

First I want to check this circuit for hold-time violations. And then I want to calculate the latency.

What exactly is tccq and tpcq of FlipFlops? I understand that tcd+tccp > thold for the hold-time to be not violated. First I would look for the shortest path. This would be from the FF "D" to the FF "F". The tccq of which FF (D or F or both?) do I have to take in consideration?

\$\endgroup\$
1
\$\begingroup\$

\$t_{pcq}\$ is the clock to Q propagation delay of a flip-flop. That is the amount of time to propagate the value at D to its Q, after a rising edge clock edge has appeared. Known as simply propagation delay or clock to Q delay.

\$t_{ccq}\$ is the amount of time needed for an initial change in output Q, due to the input D, after a rising edge clock edge has appeared. Known as contamination delay.

\$t_{cd} \$ and \$t_{pd} \$ are same things. But the terms used for combinational gates.

enter image description here

enter image description here

So \$t_{pcq}\$ = sum of \$t_{ccq}\$ and the amount of time for the output Q to become stable and valid, since the initial change occured. Same for \$ t_{pd} \$ and \$t_{cd}\$.

Suppose a flip-flop A launches the data and flip-flop B captures it.

  • For no setup violation in the flip-flop to flip-flop path, $$ t_{pcq(A)} + t_{pd} + t_{setup(B)} < T_{clk} + t_{skew} $$

  • For no hold violation in the flip-flop to flip-flop path, $$ t_{ccq(A)} + t_{cd} > t_{hold(B)} + t_{skew} $$

In your circuit, skew is taken zero.

To check for hold violation, consider the shortest path. It is from Q through AND and OR:

Like:

enter image description here

To check for setup violation, consider the longest path.

enter image description here

Now from the above expressions, I think the answer is self-explanatory.

\$\endgroup\$
  • 1
    \$\begingroup\$ Thank you: That means for my example above: tccq(D) + tcd(AND) + tcd(OR) = 1+1+1=3ns > thold(F). Is this correct? And also want to calculate the latency: t_pd(NOT) + t_pd(AND) + t_pd(OR) + t_pcq(A) + t_setup(F) = 15ns Is this correct? Did I choose the right FlipFlop delays for the calculations? \$\endgroup\$ – Nime Feb 23 '18 at 15:26
  • \$\begingroup\$ yea that's it.. \$\endgroup\$ – Mitu Raj Feb 23 '18 at 15:48
0
\$\begingroup\$

In simple terms:

The parameters describe the time delays immediately following the clock edge. Tccq happens first and is the time delay from the clock edge until the Q output might not have changed but is potentially unstable. Tpcq is the total delay that includes Tccq and any additional unstable period, after which the Q output is guaranteed to be stable.

Text book definitions:

Tccq: Contamination delay. The time after a clock edge that the Q output might be unstable.

Tpcq: Propagation delay. The time after the clock edge that the output Qs are guaranteed to be stable.

Full article: (Chapter 3, p64) http://sceweb.uhcl.edu/koch/ceng5133/notes/ch3.pdf

\$\endgroup\$
  • \$\begingroup\$ Thank you for the responce. I don't understand, what the FlipFlops ("A"-"D") at the beginning are doing and what their purpose are, what theier effects are on timing and most importantly what theier effects are if I wanted to calculate the latency. If I ignore the FlipFlops at the beginning: t_pd(NOT) + t_pd(AND) + t_pd(OR) + t_pcq("F") + t_setup("F") = 15ns \$\endgroup\$ – Nime Feb 23 '18 at 14:44

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.