How to send logic low to LVDS?

Question

I have a chip that takes LVDS inputs. It has a very large number of inputs and I'd like to set most of them to zero (or one) while prototyping. They can't be left open/floating.

What is a good way to send a fixed LVDS logic value to a bunch of pin pairs? (probably using passives, or a driver that can drive multiple differential pins at the same time)

The chip uses LVDS1.8, the datasheet looks like this:

Parameter                                         | Min | Typ | Max  | Unit
Input Common-Mode Voltage Range, VCOM             | 825 |     | 1575 | mV |
Logic High Differential Input Threshold, VIH_DTH  | 175 |     | 400  | mV |
Logic Low Differential Input Threshold, VIL_DTH   |−175 |     |−400  | mV |
Receiver Differential Input Impedance, RIN        |  80 |     | 120  | Ω  |
Input Capacitance                                 |     | 1.2 |      | pF |
LVDS Input Rate                                   |1250 |     |      |MSPS|
LVDS Minimum Data Valid Period                    |     |     |  344 | ps |

Can I just use two adjustable supplies set to 1200mV-200mV and 1200mV+200mV, and connect all the P pins together to the high voltage and the N pins to the low voltage? What current would I expect per pin pair?

Answer 1

The differential input voltage will have a nominal average signal level of 1.2 V.

To supply a constant value, just drop a 100 Ω resistor across each pair, and source 12 mA through each. Make sure you add an additional 100 Ω before the first pair, and after the last so that no input is connected directly to V_CC or ground.

This is from the TI SN65LVDS4 datasheet (the receiver I typically use).

One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that the output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range. Open circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, TI recommends to have an external failsafe solution as shown in Figure 20. In the external failsafe solution, the A side is pulled to VCC via a weak pullup resistor and the B side is pulled down via a weak pulldown resistor. This creates a voltage offset and prevents the receiver from switching based on noise.