I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using create_clock for now.
I have a slack of about 10ns in the design at present. The design contains a Nios II connected with a custom design which is rather a complex design with multiple levels of hierarcy. Provided that I want to find the worst case path inside my custm design starting from a certain block and thus including all things under it (in hierarchy), how would I do that in TimeQuest? Is it possible? At present, the timing bottleneck seems to be the Nios II.