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I have written RTL description of a circuit in VHDL which is hierarchical and I am using Altera Quartus II; my design meets timing. I had set 50MHz clock frequency (20ns period) constraint using create_clock for now.

I have a slack of about 10ns in the design at present. The design contains a Nios II connected with a custom design which is rather a complex design with multiple levels of hierarcy. Provided that I want to find the worst case path inside my custm design starting from a certain block and thus including all things under it (in hierarchy), how would I do that in TimeQuest? Is it possible? At present, the timing bottleneck seems to be the Nios II.

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Even if you can find it, it is unlikely to be meaningful information: the tools stop optimizing the timing as soon as it meets the requirements (clock frequency). If you want to know the top speed of your design, or want to see where you should start optimizing further to make it work at higher clock speeds, you should synthesize your component independently, progressively increasing the clock speed until it no longer meets timing. Then you can look at what paths cause it to fail timing.

It won't exactly match the combined design since the I/O placement and available placement options won't be the same, but generally the critical path will be in the same part of the design. Sometimes, after integrating your component into a large design the critical path can change because for some components there are only very suboptimal placements left; I've mainly seen this happen for block ram. But there's nothing you can do about these cases other than looking at the specific combined design.

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  • \$\begingroup\$ Ok, so I should synthesize only the complex custom logic block and use all virtual pins when doing full compilation. \$\endgroup\$ – quantum231 Feb 26 '18 at 10:49

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