I have a piece of memory which I need to access cell by cell:
parameter RAM_LENGTH = 1024; reg [7:0] mem [RAM_LENGTH - 1:0];
I need to iterate cells sequentially. It looks like there are at least two ways to do this. The first approach is to index memory as if it were C array of bytes:
reg [7:0] ram_addr = 0; reg [7:0] current;
current = mem[ram_addr]; ram_addr = ram_addr + 1;
This is cheap for CPU. But what if Verilog builder will attempt to build a 1024 channel 8 byte width multiplexer for me? This would be a digital circuit of tremendous size that this memory may not deserve. Or is the Verilog builder smart enough to implement access by index more reasonably?
The alternative approach would be to shift the cells every time the value is needed:
current <= mem; for (i = 1; i < RAM_LENGTH; i++) mem[i] <= mem[i-1];
in this case, I would hope from the builder to generate a shift register rather than overgrown multiplexer, as all values that define the loop are constants.
Which approach is more reasonable and would be typically used by an experienced Verlilog developer?