The Baker clamp uses carefully selected Schottky to raise Vce >Vce(sat) and Silicon diodes to raise Vce(max) and to lower BC pF somewhat like a Schottky Transistor used in 74Sxx and 74LSxx but at the expense of Pd drop like a Darlington. This raises the VI product while also raising the transition frequency.
Most recent IC to use this I know is here. http://home.mira.net/~gnb/audio/lme49810.html
It is important to realize when rCE drops to conduct more current, the equivalent Collector capacitance Cce and storage charge increases which is an RC=T (approx. limitation) . The same is true in cascading power FETs with T=RonCoss and RgCiss so there becomes an optimal critical ratio of Ron/Rg for fastest yet efficient speeds . In slow SMPS it is common to see Ron/Rg be 1000:1 where in fastest high power FET designs this sometimes reduces to 10:1 in Ron Input driver/Output driver ratios.
This is also apparently true in optimized Baker designs where the Ic/Id has been suggested around 4:1 which to me implies a component power ratio of each.
Perhaps as well just as ESR*Pd(max) =1 is somewhat a design constant in all diodes with some reduction from 1 to 1/2 due to improved SMT thermal design and some rising to 1.5 due to poor bulk resistance which accounts for all the tolerance spreading of Vf/If at rated current tolerances often to +-50%.
I realize this is more than you asked for, but I thought others may find useful. If not voted as useful, I may reduce my answers in future. (Typing on an iPod is hard,with frequent incorrect spelling subs. but then I can be resting on the beach!)