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I'm studying for the best practice to route a switching dc to dc step down regulator. Particularly this TI part.

On page 37 there's a layout example. I was wonder if it could be any problem to place vias in the whole Vout line and not only after the output capacitors.

I upload a photo.

Due to limited space I've placed the output circuitry both in top and bottom sides of pcb. I hope this won't hurt stability or something.

First, I placed the vias only in the points are necessary. After the inductor to transfer the power at the bottom layer and after the output capacitors to transfer the power at the inner layer.

But, I do not know if the extra vias (these I marked with golden color) in the output line are prefered.

Also, Is there any harm to connect the inner layer (which delivers the 5V output) to the vias at the inductor-capacitors point?

I added one more picture to be more clear of my two considerations. Red dots are vias

EDIT: I upload one more photo of my final draft layout. The part I'm still confused is the via placement. I don't know if the output line 5V must have vias in the whole plane like I did or must be placed only after the output capacitors (see photo 2, A and B). enter image description here enter image description here

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  • \$\begingroup\$ Yes shunt vias will reduce ESL but add some pF. You may compute effects of Q and SRF \$\endgroup\$ – Sunnyskyguy EE75 Feb 26 '18 at 18:07
  • \$\begingroup\$ What do you mean ESL? Any source for further reading? \$\endgroup\$ – MrBit Feb 26 '18 at 18:13
  • \$\begingroup\$ Like ESR but L each via has inductance and capacitance if near gnd plane but can be a low or high impedance transmission line root(L/C.) Computation needed. It may depend on dead time as dV/dt and dI/dt result from dZ/dt which induces ringing hence SRF. Consider ferrite beads too \$\endgroup\$ – Sunnyskyguy EE75 Feb 26 '18 at 18:35
  • \$\begingroup\$ I don't see good grounding at all. GND is the most important for a switcher. The Input cap, output caps and center slug GND should all be tied together on a top layer very thick (filled polygon) GND fill (just like in the example). This net has very spiky high currents. With your layout, you will be forcing these to longer paths and throug vias and will have high voltage spikes during the switching transitions. \$\endgroup\$ – Vince Patron Feb 26 '18 at 19:08
  • \$\begingroup\$ Of course, this is not the final design, it's just an initial component placement. Many things and connections are missing by now. I just uploaded a screenshot because I was confused about the output circuitry. As the first image describes I have two plans in my mind. I have seen both of them (A and B) working nice without any problem but I'm asking to understand what tactic is superior to another and why. \$\endgroup\$ – MrBit Feb 26 '18 at 19:15
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Via placement should be of least concern here. The biggest problem in your layout/placement is that high-current loops are forced across planes (top and ground) via extra vias. Look again at the manufacturer's suggested layout: all high-spikes loops are closed into the same ground pad, top layer, and under the chip. All are tightly localized around the control switcher. In your design, the current must pass between layers (and along the signal ground), and inductance of vias will likely increase ringing, and EMI from your layout will be horrible. Please be less inventive and try to follow the suggested layout as close as possible, including suggested BOM. It will save you a lot of troubles.

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