I am trying deserialize data that come out of a LM98640 into 14 bits words:
Attached you can find a figure of the signals out of the LM98640. http://www.ti.com/lit/ds/symlink/lm98640qml-sp.pdf (Figure 24 page 31)
I need to deserialize the signals TXOUT1 and TXOUT2:
A differential clock (TXCLK) is also output with transitions aligned with the center of the data eye. Data rates range from 80Mbps up to 640 Mbps.
(TXOUT1 and TXOUT2 changes as fast as a 640 MHz clock)
What kind of FPGA should i use to work at these rates?
Can i use flip flops to capture the data and a 14 bit wide shift register to pack this into words of 14 bits wide?
Or is it more complex at these rates? Am i going to face metastability problems since i assume a will be facing crossing time domains between the clock sampling the DATA out of the LM98640 and the clock of the FPGA.
The data deserialized is going to be provided to a NI DAQ or stored in a RAM.
What kind of xilinx FPGA should i use?
Thank you for your help