I am trying deserialize data that come out of a LM98640 into 14 bits words:

Attached you can find a figure of the signals out of the LM98640. http://www.ti.com/lit/ds/symlink/lm98640qml-sp.pdf (Figure 24 page 31)

I need to deserialize the signals TXOUT1 and TXOUT2:

A differential clock (TXCLK) is also output with transitions aligned with the center of the data eye. Data rates range from 80Mbps up to 640 Mbps.

(TXOUT1 and TXOUT2 changes as fast as a 640 MHz clock)

What kind of FPGA should i use to work at these rates?

Can i use flip flops to capture the data and a 14 bit wide shift register to pack this into words of 14 bits wide?

Or is it more complex at these rates? Am i going to face metastability problems since i assume a will be facing crossing time domains between the clock sampling the DATA out of the LM98640 and the clock of the FPGA.

The data deserialized is going to be provided to a NI DAQ or stored in a RAM.

What kind of xilinx FPGA should i use?

Thank you for your help

  • \$\begingroup\$ Why don't you use a TI LVDS deserializer? \$\endgroup\$
    – Andy aka
    Commented Feb 27, 2018 at 17:30
  • \$\begingroup\$ What is a TI LVDS? \$\endgroup\$
    – the dude
    Commented Feb 28, 2018 at 12:26
  • \$\begingroup\$ Texas Instruments is TI and LVDS is the output spec of the LM98640. \$\endgroup\$
    – Andy aka
    Commented Feb 28, 2018 at 12:28
  • \$\begingroup\$ Okay, well i need to design an FPGA for the deserialization and it has to include other specific functionalities that i need to code, i can't use a preexisting component \$\endgroup\$
    – the dude
    Commented Feb 28, 2018 at 13:30

1 Answer 1


640Mb/s DDR is a bit quick for fabric logic, but may be manageable with a DDR configured IO block in a reasonably fast part.

However every even semi recent xilinx part has an ISERDES available on the inputs, and these are more then quick enough to deal with 640Mb/s DDR mode data even in speed grade 1.

I note that your chosen ADC is radiation hardened, if you need it, that may well be a bigger issue then link speed as it will massively reduce your FPGA (And configuration device) options. If you don't need rad hard, there are probably far cheaper ADCs that would get it done.

What FPGA, depends on what you need, I would go 7 series just because that gets you Vivado as a tool chain that is getting more love then ISE (Also its constraints file format is less annoying IMHO).

  • \$\begingroup\$ Thank you for your answer, i will check the ISERDES and try to figure out how it works and how to use it \$\endgroup\$
    – the dude
    Commented Feb 27, 2018 at 16:45
  • \$\begingroup\$ I just read that when using the ISERDES there where minimum data rate considerations, does that mean that i will have to change my architecture depending if the rate is 80Mbps or 640 Mbps? \$\endgroup\$
    – the dude
    Commented Feb 27, 2018 at 17:43
  • \$\begingroup\$ At 80Mb/s you are hardly going to need the serdes are you? Actually you could probably just undersample the serdes output, if you want to leave the block in line all the time, but you would probably have to reprogram the PLL to suit. \$\endgroup\$
    – Dan Mills
    Commented Feb 27, 2018 at 18:00
  • \$\begingroup\$ Thanks, i have been reading this document xilinx.com/support/documentation/application_notes/xapp1064.pdf And it is written that the ISERDES designs are for use in source-synchronous systems where the data and clock are edge aligned. Whereas is my case a differential clock (TXCLK) is output with transitions aligned with the center of the data eye \$\endgroup\$
    – the dude
    Commented Feb 28, 2018 at 9:43

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.