You posted a corrected version of the schematic in another question (which has now been deleted) with important differences (e.g. no battery). I reproduce it below:
Essentially, the circuit in the red box ensures that the circuit is only turned on when C1 contains sufficient charge:
- The piezo power source charges C1 through the bridge rectifier.
- During this initial phase, Q2 is off and the MAX666 and subsequent circuits are off.
- Zener D2 is biased through R4 and R3, limiting the base of Q1 to about 12V, while C1 will charge to a higher voltage.
- When C1 reaches about 12.6V, Q1 base-emitter starts conducting, bringing Q1 on.
- The current through Q1 collector goes through R2, giving a voltage drop which turns Q2 on.
- The "gnd" for the rest of the circuitry is now connected to C1's negative plate via Q2 and thus the circuit is powered (with MAX666 providing 5V regulation).
So Q1,D2,Q2 hold the system off while C1 charges to an appropriate voltage.
Now what is C3 for?
- If C1 starts to lose charge/voltage, the MAX666 Vin and Vout will droop, causing improper circuit function. To prevent this, the MAX666 grounds the LBout pin (see What does "LB" out mean in a DC-DC buck converter?).
- The LBout low pulse is transmitted through C3 and momentarily turns Q1 off.
- This pulse is enough to break the "latch" action formed by Q1 and Q2, and Q2 turns off. The capacitive coupling (C3) ensures that Q1 is not held off forever.
- The rest of the circuit goes back to being unpowered, while C1 regains its charge, and we go back to step (1).
Edit in response to question:
The VN2222L NMOS has a Vgs threshold of about 2.5 V. This voltage will be created by a tiny current of 2.5 uA through R2.
So as Q1 turns on (allowing current from C1 to flow through R1,Q1,R2), Q2 will also start to turn on. This has a feedback effect because Q2's conduction lowers the voltage at Q1's base, thereby turning Q1 on strongly, which turns Q2 on more strongly. This is the "latch" effect which must be broken for the circuit to reset to step 1.