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I need to receive 42 pairs of LVDS signals to a FPGA. All i want is that the FPGA converts the differential pairs in normal std_logic signals. And i need to choose a xilinx FPGA with enough pins that support LVDS signaling. I'm a bit confused and don't know which kind of FPGA to choose depending on the standards I/O LVDS or LVDS_25 I don't really know how the standards work or how do they convert the signals Any help would be much appreciated Thank you

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  • \$\begingroup\$ If you want a Xilinx FPGA, go to the Xilinx website, look at the information for the various FPGA families, pick one that can go fast enough, then pick one with enough pins. Shopping questions are off-topic on EE.SE. \$\endgroup\$ – Tom Carpenter Feb 28 '18 at 16:48
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    \$\begingroup\$ @TomCarpenter This isn't a shopping question. He's just asking about the Xilinx IO standards for LVDS which are in fact quite confusing. See my answer in a minute. \$\endgroup\$ – jalalipop Feb 28 '18 at 16:50
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    \$\begingroup\$ Possible duplicate of deserializing high speed data \$\endgroup\$ – Andy aka Feb 28 '18 at 17:38
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LVDS and LVDS_25 are most likely electrically the same. I don't know which family you're looking at, but in the Spartan-6 there are also two LVDS standards, LVDS_25 and LVDS_33. They are electrically the same (see below from DS162), so they will work the same as far as interfacing with other LVDS parts. The distinction is that you use LVDS_33 when your bank voltage is 3.3V and LVDS_25 for 2.5V.

You can confirm this by looking at the input and output levels in the datasheet of the part you're evaluating.

enter image description here

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  • \$\begingroup\$ Thanks this is helpful, by bank voltage do you mean at what voltage the alimentation of my component is? My LVDS pairs signals are the outputs of a LM98640 and in the DATASHEET of this component it is written that the supply voltage is: Supply Voltages: – 3.3V Nominal (3.15V to 3.45V Range) – 1.8V Nominal (1.7V to 1.9V Range) \$\endgroup\$ – the dude Mar 1 '18 at 9:24
  • \$\begingroup\$ I checked in the Spartan 7 data sheet there is only the LVDS_25 standard does that mean i can't use it if my bank voltage is 3.3V? \$\endgroup\$ – the dude Mar 1 '18 at 9:32
  • \$\begingroup\$ Bank voltage refers to the voltage you are supplying a particular FPGA IO bank with, in the case of LVDS it is independent of the voltage your component at the other end of the link uses (Provoding you check the LVDS common mode range is acceptable). The 7 series parts have HR and HP banks, with maximum bank voltages of 3.3 and 1.8V, either of which will work with LVDS receive, but voltages for transmit are more constrained (2.5 and 1.8 IIRC). Note that the internal rx termination resistors are also only qualified for some bank voltages, see xilinx.com/support/answers/43989.html \$\endgroup\$ – Dan Mills Mar 1 '18 at 10:50
  • \$\begingroup\$ I'm trying to connect the LVDS outputs of a LM98640 to an FPGA, i've read the xilinx.com/support/answers/43989.html and for example for the diagram of the LVDS_25 standard, for the branch input i need to check VCCO VID VICM VOCM VOD i'm not sure to which component these voltages refer to? to the FPGA or to the LM98640? In the datasheet of the LM98640 there are two supply voltages of 3,3 V and 1.8V and the differential output voltages of the LVDS outputs are from 275mV to 590 mV. \$\endgroup\$ – the dude Mar 1 '18 at 15:15
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    \$\begingroup\$ @thedude Wow so I haven't looked at Spartan-7 much but it does look like you can't transmit LVDS with a 3.3V bank. As far as your questions about parameters: VCCO applies to the FPGA, and it should be 2.5 V to use LVDS_25. VID applies to the receiving end (sounds like the FPGA in your case), and VOD the transmitting end. VOD should fall within the range given by VID. Same with VOCM and VICM, the output parameter needs to fall within the range of the input parameter. In general they will always be compatible but it's good to check just to understand what's happening. \$\endgroup\$ – jalalipop Mar 1 '18 at 18:41

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