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I am trying to design with the NCV5183 with a 400V DC bus. I am trying to figure out the creepage/clearance standards i need to consider for high voltage layout and if the IC's pin to pin spacing is ok for a 400V application. Does the IEC60950 or any other standard define what spacing for the voltage that i am working with. Does this requirement only apply for spacing between high voltage nodes. Does it also apply to spacing between high voltage and low voltage nodes. If you check in the datasheet Pin 6 (HB) is next to VCC which will be at a much lower potential.

http://www.onsemi.com/pub/Collateral/NCP5183-D.PDF

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To avoid creapage currents spacing alone is not good enough. Many board houses can do slot cuts as narrow as 31 mils, or .031". I worked at a surge suppression plant where most all boards had 120 VAC to 600 VAC at one end, and 5 VDC for diagnostics.

The key is to slot-cut under opto-couplers and between phases, next to the lead with the high voltage. This way, with a conformal coating of polyurethane added, the high voltage is 'trapped' at its point of entry.

This includes resistors and capacitors that tap into the high voltage for various reasons. Most slot cuts are 1 cm or 3/8 inch long at most. Yes, they do charge for slot cuts, but it is worth it because if a 'mains' feed to the board starts to arc from creapage, it will quickly turn into a plasma ball that will burn a hole in steel in 1/4 of a second.

If soot leaks to other phases on a split-phase or 3 phase board it quickly becomes a bomb.

There were no standards for this, so the chief engineer played it safe and isolated any high-voltage with slot cuts, even some 'L' shaped cuts. Conformal coating was part of our standard procedures once a board passed testing.

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