# Flyback simulation - not regulating at lower load

So I've been trying to simulate a flyback converter with the full load condition of 10v, 10A (100W) at the output at fs = 80kHz. The design equations I used were from "Pulse-Width Modulated DC-DC Converters" by M. Kazimierczuk. Given that my input range is from 180Vrms to 230Vrms, I wanted the flyback to regulate the output at 10V from 0 to 10A. My simulation circuit is shown below. My output voltage is shown below for both 1ohm load and 100ohm load. 1ohm is to simulate the 10A output while 100ohm is to simulate a much lower load (0.1A).  Since V1 is supposedly from the controller IC and there is no feedback here yet, it is an open loop system. I basically adjusted the duty cycle of Q1 gate signal to get my desired output. 325v at the input is assumed to come from the previous rectifier stage with 230Vrms input (high line). At full load (10A), duty cycle is around 30% to achieve voltage regulation (10v). But at 0.1A output, I can't seem to regulate the output, even if I drop the duty cycle as much as I can. The output waveform I've shown for 0.1A has a gate signal for Q1 with 5% duty cycle.

L2 was the magnetizing inductance, and since I want to design the flyback in DCM, I calculated that Lmax = 546.4uH. Anything higher than this can possibly make the flyback operate in CCM. So I chose Lm = 500uH. L1 was just there to simulate some leakage inductance.

The number of turns n = N1/N2 = 16.78. So I chose 17 in this case. The mosfet and diode are chosen such that their ratings are higher than my calculated max current and voltage across them.

Any suggestions on where do I start to fix this?

• You have no feedback loop so how can your possibly expect it to regulate? Also your leakage inductance in in parallel with the magnitizing dito. It must be in series. Mar 1 '18 at 8:05
• For light loads reduce the frequency as in switch to PFM mode with the smallest fixed pulse width. Jul 13 at 1:41

Flyback regulators are power regulators that give the impression of voltage regulation when used within a closed loop that can alter the duty cycle. With your lower limit at 5% you might hit problems at light loads as you are seeing.

The output waveform I've shown for 0.1A has a gate signal for Q1 with 5% duty cycle.

In the power transfer, you charge an inductor (P1||L2) with energy and that energy is proportional to duty cycle squared. This is because the current is proportional to duty cycle ($V\cdot t/L = i$) and stored energy is proportional to current squared ($W = \frac{Li^2}{2}$).

Given that your maximum power is 100 watts and your minimum power is 1 watt, you might need to rethink what the PWM limits are if you are using 50% duty for the maximum power scenario. At lower duties the core may not be saturating as muchs and this would increase the power transferred. I would suggest you try and get down to 1% duty cycle and see what happens.

If maximum power is acheived at 25% duty then you would need to get below 2.5% duty to achieve voltage regulation with a 1 watt load and probably much less if you are close to core saturation on higher powers.

The magnetic component in the flyback converters is a coupled inductor, not a transformer.

As you might know, the primary inductor stores an energy when the switch is on; then transfers this energy (totally or partially - that is where the DCM and CCM terms come from) to the secondary when the switch is off.

Now first think about the stored energy in the primary: It is constant due to the constant duty-cycle. This energy induces a voltage across and a current through the load.

So, since there's no feedback (i.e. regulation mechanism) provided, the lesser the load resistance, the lower the output voltage induced. Likewise, the higher the load resistance, the higher the output voltage induced.

There's also one thing should be considered: Flyback, Forward, Half- or Full-Bridge converters need a minimum load for proper operation. In my designs, especially in low-power ones (Po <= 100W), I keep this dummy load at 1-5% of the full load. But please note that, this value depends on the design as well.

Even if you close the loop via a feedback mechanism, there's still a chance to enter DCM due to the light- or no-load. And at light load state, discharging duration will be low thus the output voltage will be high again. So, adding a dummy load might be a solution to this but brings extra power waste.

Using an active switch (e.g. MOSFET - please Google "Synchronous Rectifier") at the secondary is also a solution. This will help reducing the output voltage at light loads by allowing the current to flow back and forth (The diode at the output does not allow this). But this brings extra complexity.

• I am constantly changing the duty cycle of the gate signal, so isn't that what PWM controllers do? I just want to simulate a regulated output by me changing the duty cycle for different loads. I know that a closed loop is needed for the actual implementation. I am planning to use an optocoupler and a PWM controller. For example, given the 1ohm load, I got around 30% duty cycle in order to regulate Vo to 10v. But with 100 ohm load, I cant seem to regulate the output to 10v even if I change the duty cycle to low values. Mar 1 '18 at 9:03
• I am constantly changing the duty cycle of the gate signal Based on what input? The DuCy should change depending on the output voltage. Without doing just that, there is no output voltage regulation. Mar 1 '18 at 9:48
• @user139731 I've edited my answer. Mar 1 '18 at 9:56

A 5% min PW at 80kHz = 6.25 us will work better at low loads by reducing the fs towards 20kHz. Since the load RC =T is 100x the minimum , reducing the the fs by 8 with PFM control or skip pulse method, the output ripple should not be worse.