Design each to have the same Vgs(th) at 1.5V and similar RdsOn (although Nch tends to be lower. (Vt is 1.5 for CD4000 Logic I recall)
Verify by measuring input voltage and supply current and self bias with a 10k negative feedback R , It can be 10M but then DMM will load it.
Then verify transfer function with and without load and see the change.
- Fix the NMOS dimension
- Vary the PMOS width until it will give you the same current as the NMOS at |VGS|=VDD/2. The PMOS width is usually 2-3x more than the NMOS due to ratio of hole and electron mobility.
Note that it will only be precise at only one supply voltage, temperature value and one process corner, without taking into account statistical shifts due to mismatch. Also, an inverter has other specs than the threshold voltage. Threshold is just of them. (propagation delay for given drive and load, ride and fall times for a given load and their symmetry, minimum/maximum supply)