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I want to simulate an inverter with CMOS. When I added a load capacitance and plotted the output voltage. I saw a sharp voltage graph so I have changed the dimensions of the transistors and got the graph that is shown below.

enter image description here enter image description here

What is happening when I am adding a load capacitance?

Here is the circuit with capacitance:

enter image description here

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  • \$\begingroup\$ It takes time to charge up, is that surprising? \$\endgroup\$
    – jramsay42
    Commented Mar 1, 2018 at 10:28
  • \$\begingroup\$ Yes, because I have started to learn two weeks ago. And I do not have enough background but I am trying to catch up ... so I need help to understand some basic stuff. If you can explain I will be extremely glad. \$\endgroup\$ Commented Mar 1, 2018 at 10:33
  • \$\begingroup\$ Google RC circuits, there are hundreds of sites with far better explanations than I could give you. \$\endgroup\$
    – jramsay42
    Commented Mar 1, 2018 at 10:34
  • \$\begingroup\$ What were the transistor dimensions for the top graph? \$\endgroup\$
    – Dave Tweed
    Commented Mar 1, 2018 at 11:33
  • \$\begingroup\$ You discovered why people want as little capacitance as possible. Capacitance slows down the circuit as it takes time to charge the capacitor and that steals from your output. In the top graph the capacitance is OK but in the bottom it is too large for your signal frequency and you never reach a stable output. \$\endgroup\$ Commented Mar 1, 2018 at 11:44

1 Answer 1

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When you add a capacitor, it charges via the pull-up PMOS to output a logic '1'. If the PMOS has a definite ON-resistance, R and if the capacitance of the capacitor = C, RC time constant will decide the rise time while driving output '1'. That's why that slope is there.

Similarly, the capacitor discharges through through the pull-down NMOS to drive the output to logic '0'. The ON-resistance of NMOS will decide the RC time constant this time, and hence the fall time to reach logic '0'.

The dimensions of the transistors will decide its resistances. W/L ratio of PMOS to NMOS is typically kept at 2.5 to achieve equal rise and fall times.

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