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I am using the MCP3248 4 input ADC with built in PGA and reference in a design and have determined that it has a small gain error versus a precision volt meter. The error is within the tolerance from the datasheet. The strange part is that the gain errors are different for the 4 channels. My design is such that gain errors cancel out if they are consistent across all channels, so the non-matched gains are an issue. I would like to avoid having to do calibration.

Is different gains on different channels standard for all MUX/PGA type ADCs or is it just the way that this part is designed? I would have thought that the chip would be designed with a 4:1 MUX followed by a PGA and ADC, but it seems with the different gains that it might actually have 4 PGAs followed by a 4:1 MUX to the ADC. Is there some reason why it would have been designed that way?

In order to give you an idea of the scale of the difference, 1.0029 and 1.0075 are the correction multipliers required for two different channels to match the value read by a precision volt meter.

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  • \$\begingroup\$ good question. the Self Calibration of Internal Offset and Gain per Each Conversion seems to cause this.. Did you alert Microchip forum? Typ spec given ONLY 0.1% \$\endgroup\$
    – D.A.S.
    Commented Mar 1, 2018 at 21:59
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    \$\begingroup\$ is there no other way to share the same channel? What is your gain match tolerance? \$\endgroup\$
    – D.A.S.
    Commented Mar 1, 2018 at 22:06
  • \$\begingroup\$ I think the best solution is to just add an external SPDT analog switch so that the two signals for which the gain matters go into the same channel. It would have been nice to avoid the extra part. \$\endgroup\$
    – crj11
    Commented Mar 1, 2018 at 22:44
  • \$\begingroup\$ What is there about a "typical" that means "guaranteed"? A different package, a different PCB, will cause different errors because of ringing that couples into the ADC and the analog comparator, during sampling or during the binary-search-algorithm execution. \$\endgroup\$
    – analogsystemsrf
    Commented Mar 1, 2018 at 23:35
  • \$\begingroup\$ I did check out Microchips forums, but the only ones I could find were for their embedded products, not their analog line. \$\endgroup\$
    – crj11
    Commented Mar 2, 2018 at 4:14

2 Answers 2

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According to the datasheet it does indeed have a mux and a single PGA - as well as a single ADC.

enter image description here

I know that still doesn't tell you why the channels respond differently.

I thought it would be good to verify how the thing works before we go off chasing the wrong thing.

So, now we know it can't be a mismatch in gains on the PGAs because it only has one.

Can't be a mismatch between ADCs - again there's only one.

Might be some slight differences in the mux channels.

Might be some differences in the impedance of the circuit outside the chip - whatever signal you are feeding it.

Might be something else entirely, but I sure don't know what.

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  • \$\begingroup\$ To investigate whether it is perhaps related to the sources driving the ADC, I swapped the inputs and changed the test code to reflect this. The results were slightly different and not as good as the unswapped version. Still much better than the uncorrected version, however. \$\endgroup\$
    – crj11
    Commented Mar 2, 2018 at 4:12
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Change the Sample timing, to allow 2X more time in acquiring the external voltage onto the silicon-based sample cap. If doping is marginal, the onchip anti-alias resistors (or the analog MUX on-resistance) may be degrading the time constant.

Another approach: temporarily raise the VDD by 0.5 volts, and examine the accuracy. Higher internal logic drive to the analog mux FETs will reduce the R_on and allow faster settling.

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