Following is the analysis I have done for the circuit:
This circuit is a part of the shift register and I am posting only a section which is required for the analysis (By the way, D flip-flop (74LVC1G80) is powered to 3.3 V ) and the output D is connected to another D-FF (74LVC1G80) using R(1 K Ohm) - C(20 pF) filter and so on.
Data signal, Din: Frequency = 400 kHz, voltage range = 0 – 3.3 V
Clock signal, CLK = 12 Mhz.
D-FF input capacitance = 3.5 pF
My intention is to analyze the RC filer and find the input voltage V at the pin D.
Figured out that the purpose of the RC filter is to provide sufficient hold time. But I was trying to understand how the hold time will be improved with an RC circuit at the input and how I can I calculate the hold time mathematically. Guessed in this way, the data logic high or low will stored in the capacitance (20 pF) and this will be available to the D-FF, thus enough hold time. Basically I am not convinced with it and unfortunately there is no reference for this case from google as well, kindly share your views about the purpose of RC filter and how to calculate the hold time.
What will be the maximum voltage (V) at pin D.
See the voltage division approach,
$$V_{max} = V_{Din} \frac{ X_{C\text{(20pF)}}}{ X_{C\text{(20pF)}} + R_{\text{(1k)}}}$$
If I take the voltage division rule, how it is going to be wrong, what is the criteria to select the VD rule?
Another approach:
$$ V_{max} = V_{Din} ( 1 – e ^ \frac{-t1}{R_{\text{1k}} C_{\text{20pf}}})$$
When can I use this formula over the VD rule? How can I select the time t1?