Hold time and voltage maximum analysis for D flip-flop?

Question

Following is the analysis I have done for the circuit:

This circuit is a part of the shift register and I am posting only a section which is required for the analysis (By the way, D flip-flop (74LVC1G80) is powered to 3.3 V ) and the output D is connected to another D-FF (74LVC1G80) using R(1 K Ohm) - C(20 pF) filter and so on.

• Data signal, Din: Frequency = 400 kHz, voltage range = 0 – 3.3 V

• Clock signal, CLK = 12 Mhz.

• D-FF input capacitance = 3.5 pF

My intention is to analyze the RC filer and find the input voltage V at the pin D.

1. Figured out that the purpose of the RC filter is to provide sufficient hold time. But I was trying to understand how the hold time will be improved with an RC circuit at the input and how I can I calculate the hold time mathematically. Guessed in this way, the data logic high or low will stored in the capacitance (20 pF) and this will be available to the D-FF, thus enough hold time. Basically I am not convinced with it and unfortunately there is no reference for this case from google as well, kindly share your views about the purpose of RC filter and how to calculate the hold time.

2. What will be the maximum voltage (V) at pin D.

See the voltage division approach,

$$V_{max} = V_{Din} \frac{ X_{C\text{(20pF)}}}{ X_{C\text{(20pF)}} + R_{\text{(1k)}}}$$

If I take the voltage division rule, how it is going to be wrong, what is the criteria to select the VD rule?

Another approach:

$$ V_{max} = V_{Din} ( 1 – e ^ \frac{-t1}{R_{\text{1k}} C_{\text{20pf}}})$$

When can I use this formula over the VD rule? How can I select the time t1?

Answer 1

This approach is not going to work. You have no relationship in your circuit between the 12 MHz clock, and the incoming signal (which I assume is a nominal square wave, but this doesn't change much).

This means that for any particular input edge, you have no idea where the clock edge will fall, and if you will see a setup/hold violation.

The correct approach here is to cascade your flop with another flop. Although the first flop may not get a clean input, it will resolve to one of the two legal states. The second flop then gets a dramatically improved setup/hold at it's input. The cost here is increased latency - it takes 2 clock cycles on average to sample the input change (could also be 1 or 3).

Metastability affects the flops flowing this one more significantly than the capture flop.

Answer 2

If the 400 KHZ clock is synchronous with the 12 MHZ clock, the issue becomes the time delay set up by your RC filter. Though it is not a sine wave, the math says it creates a delay of 125 nS and a -3 dB roll-off at 7.957 MHZ. A 400 KHZ square wave has edges 1.25 uS apart, for a period of 2.5 uS.

A typical 74AC74 flip-flop has a set-up time of 5.5 nS, and a hold time of 0.5 nS, during which the 'D' input must be stable during the rising edge of clock.

With a 12 MHZ sampling rate you have a rising clock edge every 8.33 nS. With the RC values you have you should get an output that is toggling between '1' and '0' almost constantly, with a 30 HZ jitter rate. I added a drawing to include a jitter filter, also synced to the 12 MHZ clock, but with a 8.33 nS delay it will NOT pass along any noisy output from the first flip-flop.

NOTE: With a synced square wave and small values of R and C, it is possible NOT to have any jitter from the first flip-flop

^{simulate this circuit – Schematic created using CircuitLab}