# Change in PLL settling time as a result of halving charge pump current/doubling loop filter capacitor

I have a PLL that is operating unstably at some temperatures. I have been able to show that reducing the charge pump current from 128uA to 64uA ensures that the PLL will operate stably at the same temperature point where it would otherwise be unable to lock.

Rather than have a software based solution I would like to achieve the same result (a locking PLL across my temperature range) by changing the loop filter components.

----+----+----
|    |
Cs ---  --- Cp
---  ---
|    |
Rs \    |
/    |
\    |
|    |


Since halving the charge pump current was sufficient to stabilize my loop would doubling the loop filter capacitance Cp (shown above) provide the same result. Currently my component values are Cs = 3300pF, Rs = 6.81kOhm, and Cp = 33pF.

$$\Delta V_1 = \Delta V_2 = \Delta V,$$ $$i_1 = 2i_2,$$ If the period of time where the charge pump is conducting (phase difference) is fixed then $$Q_1=2Q_2,$$ $$\Delta V = \Delta Q/C$$ As a result the doubling of the value of C with the same charge pump current is effectively the same as halving the charge pump current and leaving C fixed.

I realize that this will change the loop filter bandwidth as well as impact the settling time. Is there a way of getting a rough estimate of how this will impact the settling time? I was hoping to get an answer as a delta from the existing implementation (e.g. the settling time will double.) What other impacts might such a change have to the PLL's behaviour?

• If you post a link to your schematic image, someone with the rep can edit your question to include the image. – Chris Laplante Jul 18 '12 at 0:33
• Just as a quick update. I changed Cp from 33pF to 68pF and now my loop's performance is significantly worse. I still have a ratio of ~50:1 for Cs to Cp so it's my understanding that Cp should not be making my loop unstable. – steven_p Jul 18 '12 at 17:17

Q Is there a way of getting a rough estimate of how this will impact the settling time?

A Yes but Design handbooks or Application Notes help more than analyzers as non-linear mixer affects simple 2nd order control theory. I don't have any magic formula, but some others may have equations that fit a certain design.

For example I found advice such as using Cs/Cp ratio of 10:1 good for Bode plot phase margin control once you find the best gain range.

• reducing phase margin of phase or increasing phase lag near unity loop-gain increases overshoot ( 0 margin = oscillator) Hence Cs/Cp ratio is useful for compensation to shift this operating point below 0 dB.

• Lower capture time from increased bandwidth but more phase noise.

• Lock time is also affected by SNR here gain of mixer is reduced with increasing noise.

• VCO temperature sensitivity of slope affects loop gain , which can be corrected.

• Capture range defined by F offset that can be acquired under worst-case and/or nominal conditions is affected by Loop gain sensitivity to temp. Capture range must be much less than worst case VCO error under all conditions to work.
• Total loop gain needs to be << 1 after 180 phase shift becuase when 180' shift & negative feedback (180deg) this becomes positive feedback and when close or < 1 unity gain it rings with too much overshoot, so lower gain at 180deg phase shift in the phase mixer filter is one key design criteria for minimizing overshoot.

Design tradeoffs are lock-in time, over-shoot, phase noise, noise skirts, capture range, image rejection, aliasing jitter, harmonic spurious lock.

Dual gain-bandwidth filters are desirable for fast lock-in time with low overshoot and then slow mode for noise rejection.

SNR affects gain of channel as phase error signal becomes swamped by noise and results in lower gain of mixer.

VCO can change gain with temperature, but can be compensated or stabilized with dual gain approach. Capture then lock on slow mode.

Factors that affecting temperature stability of gain of loop are temperature sensitivity of VCO Hz/V per deg'C from parts such as varicap.

• I updated the initial question with some component values that I initially left out. I do have a ratio between Cs/Cp that is 100:1. I'm comfortable with most of the design trade-offs you list (thanks) as my system is configured once at power-up and then the PLL frequency is not changed. Based on the 10:1 rule that you list and I've come across elsewhere is there any reason that you can see reducing Cp to 68pF (still a 50:1 ratio) would make my problem worse? – steven_p Jul 18 '12 at 17:20