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This is an effort to find the rise and fall time of the following circuit.

enter image description here

I have calculated the rise time and requesting confirmation from expert’s end. There are some assumed values like trace impedance parasitic capacitance, kindly note that is for the sake of calculation purpose. I am much interested how the calculations need to be done than the numerical values. But values can be updated if it is not at all close to real values.

See the details, D Flip-flop (SN74LVC1G80) is powered with 3.3 V and logic levels are 0 V (Logic LOW) and 3.3 V (logic high).

Assumed parasitic capacitance = 3 pF

Assumed trace impedance = 10 Ohm

Data switching at a rate of 500 kHz

Following method used to calculate the rise time:

\begin{align} 3.3 \cdot 0.1 &= 3.3 \left(1- e^{-\frac{t_1}{RC}}\right) &\implies t1 &= 3.1608\text{ ps}\\ 3.3 \cdot 0.9 &= 3.3 \left(1- e ^{-\frac{t_2}{RC}}\right) &\implies t2 &= 69.078\text{ ps} \end{align} So the net rise time is = 69.078 – 3.1608 = 65.9172 ps

Observations

  1. Rise and fall time is independent of the data signal switching frequency
  2. Rise or fall time can be increased by adding series resistor and parallel capacitor to the each output stage of the FF ( that is pin Q ).

Kindly confirm or point out my mistakes.

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    \$\begingroup\$ An expert would probably simulate this to make sure there is no anomaly. \$\endgroup\$ – Andy aka Mar 3 '18 at 9:16
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I don't see why you're even basing your calculations on the parasitic capacities here. The datasheet clearly says what setup and propagation delay times are, and these are three orders of magnitude larger than the time constants you're getting, so whatever you calculated there is insignificant to the working of that circuit. In other words, no, your calculation is wrong and doesn't give you the actual rise and fall times. You need to read page 9 of the datasheet, especially note G, followed by table 6.8 and 6.9 on page 7. The rise and fall time of digital circuits are not defined by the input capacitance.

  1. Rise and fall time is independent of the data signal switching frequency

well, yes, in your model of the devices it is.

That doesn't say your model is a good one: You'll find out that the real world, for rising frequencies, effects of the transistors used in the flip flops play a role.

Now, at your 500 kHz... pfft. That device is specified to work up to clock rates of 160 MHz.

Also, notice how 1 ps is in the order of 1 in 1 million in relation to one 500 kHz period. If that number was corrent, you wouldn't need to calculate any of this, for all that is practical, anything happening with less than a couple thousand of those flipflops in a row would look "instant" to anything receiving that 500 kHz tone (to get rid of transients/abnormalities, proper glitch filtering (typically, low-pass at maybe 5·500 kHz followed by a Schmitt trigger) will totally do).

  1. Rise or fall time can be increased by adding series resistor and parallel capacitor to the each output stage of the FF (that is pin Q).

Yes. Any filter has a delay. That's basics physics! Remember the Bode phase plot, and remember what phase is!

Be a bit careful, though: while you can smooth out transients with a filter and thus doing some filtering, especially when getting a signal from a "noisy" source, is often a good thing, you're also spreading out energy over time, and now rely on the input stage of your flipflop to have a very well-defined and stable threshold voltage. Without loss of generality, that's not a good thing if you want to have precise timing (or low power…).

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  • \$\begingroup\$ Any link towards the theroritical examples of rise time fall time calculation will be appreciated. Was curious to know the way do the calculation. \$\endgroup\$ – vt673 Mar 3 '18 at 20:29
  • \$\begingroup\$ To be honest, these times were simply measured! \$\endgroup\$ – Marcus Müller Mar 3 '18 at 21:43

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