It sounds like a double emphasis but indeed, pin 25 of the LTC2323 (http://www.linear.com/product/LTC2323-16) I lets me choose between:

  • CMOS (GND)
  • Low-Power LVDS (leave floating)

As often, the datasheet does not bother discussing difference at all and neither does my Google search or Wikipedia ersult in enlightenment.

I want to use "LVDS": I connect the digital lines differentially (100 Ohm terminated) to a Spartan-6 FPGA. The IO voltage is 2.5V. Shall I set the pin to LVDS or Low-Power LVDS?


As shown on page 4 of the datasheet, the voltage over the 100 Ω load resistor is smaller in low-power mode, i.e., the current is smaller:

LTC2323 LVDS output

LVDS is a standard (TIA-644). You can use low-power mode if your FPGA has a more sensitive receiver that is able to cope with 75 mV (the datasheet would tell you this).

  • \$\begingroup\$ If I want to be safe - is it OK to just configure the pin for LVDS? I.e., can all LVDS compliant receivers (e.g. Spartan 6 FPGA) also deal with "low power LVDS"? Is there any other advantage compared to LVDS other than lower current (and hence power consumption)? (In terms of supply voltage, they seem to be the same (2.5V)) \$\endgroup\$ – divB Mar 4 '18 at 9:04
  • \$\begingroup\$ LVDS is a standard (TIA-644). Low-power mode requires a more sensitive receiver (see the FPGA's datasheet). \$\endgroup\$ – CL. Mar 4 '18 at 9:08
  • \$\begingroup\$ I assume the answer to my questions are 1) yes, 2) yes ) no and use LVDS. \$\endgroup\$ – divB Mar 4 '18 at 9:15

Datasheet page 22 has the answer, one mode is single ended the other is differential.

However it doesn't state what happens when floated.

Now figure 22 shows it pulled up to 2V5 and talks about a LVDS SPI. This ties up with page 1 features where it highlights "CMOS or LVDS SPI compatible serial I/O".

To me it looks like activating this mode gives access to LVDS on the control logic rather than single ended SPI. TI have a good app note on LVDS SPI.

The datasheet though is vague about how to enable this mode, it says in on place to leave floating yet the diagram shows it pulled up. May well be a datasheet error.

  • \$\begingroup\$ This question is about the third mode, low-power LVDS, which you did not mention. \$\endgroup\$ – CL. Mar 4 '18 at 9:04
  • \$\begingroup\$ Yes I see that now having re-read it. I've adjusted the answer accordingly.. \$\endgroup\$ – Captain Barnacles Mar 4 '18 at 9:47

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