0
\$\begingroup\$

schematic

simulate this circuit – Schematic created using CircuitLab

I have a system where i need to have a clock enable for two 74LS374 D Flips that do not already have a clock enable. I have decided to use a single 2n3904 NPN BJT, with the collector connected to the clock pin, the base (through a resistor of course) connected to my enable signal, and the emitter connected to the system clock, so that when I assert enable, the clock pin will be seeing either ground or 5V. I have read online that this configuration is the wrong way to do it. Why is this?

Keep in mind that I am here because I am by no means an expert, and up until now i assumed that high base voltage means collector = emitter in an NPN. Am I on the right track or completely wrong?

Is there a better way to accomplish what I would like to do?

Thanks

EDIT: Thanks to some users for their suggestions, a simple schematic is now included. Values and part numbers are exact.

\$\endgroup\$
5
  • 2
    \$\begingroup\$ Hit the schematic button on the editor toolbar. It's very easy to use. Double-click a component to change its style and value. Schematics are much better than words. \$\endgroup\$
    – Transistor
    Commented Mar 4, 2018 at 15:14
  • \$\begingroup\$ Please can you edit your question and add a circuit diagram. Otherwise, you're expecting people to piece it all together in their head. The schematic editor there is a breeze to use. The better the quality of your question, the better the quality of the answers you will attract. \$\endgroup\$
    – TonyM
    Commented Mar 4, 2018 at 15:14
  • \$\begingroup\$ Try adding a collector pull-up resistor of maybe 1 kohm and you might be in business. \$\endgroup\$
    – Andy aka
    Commented Mar 4, 2018 at 15:32
  • \$\begingroup\$ We call this a Common Base circuit and source impedance must be < 100 ohms. It can be 0 . The benefit is high speed. \$\endgroup\$ Commented Mar 4, 2018 at 17:47
  • \$\begingroup\$ How fast is the clock? Asynch or synch with clock? How much load can the CLK line handle? \$\endgroup\$
    – jonk
    Commented Mar 4, 2018 at 19:44

2 Answers 2

1
\$\begingroup\$

I believe you are talking about this.

You would need a pull-up as shown.

schematic

simulate this circuit – Schematic created using CircuitLab

However, the issue with this circuit is, when you turn off the transistor the clock line will go high, clocking the 374 if the input clock line itself is low. That means WHEN you disable it is critical since the data you are trying to latch must still be presented and held at that time.

Further, the rising edge of the clock is dictated by the resistor so it will not be as sharp as the original digital clock. Timing and hold times will be affected. The source clock signal also needs to be able to sink the pull-up current AND the base current, so you can not make R1 OR R2 small.

Adding a proper logic gate would be much better and will prevent disturbance on the original clock line.

\$\endgroup\$
3
  • \$\begingroup\$ You say logic gate, should I just cop the loss of board space and chuck in maybe a 74LS08 quad AND? \$\endgroup\$
    – DylanG
    Commented Mar 4, 2018 at 15:38
  • \$\begingroup\$ @DylanG if it's SMT there are small single gate logic devices that are the same size at the transistor and wont need resistors. However, usually clocking devices like this is done via a mux that selects the appropriate device synchronously to the clock. \$\endgroup\$
    – Trevor_G
    Commented Mar 4, 2018 at 15:40
  • \$\begingroup\$ Unfortunately it is not SMT, my hands are just not good enough. I have a lot of logic gate chips but no muxes so I think I will go that route. Thanks for your help \$\endgroup\$
    – DylanG
    Commented Mar 4, 2018 at 15:42
1
\$\begingroup\$

Here's what my simulator shows: -

enter image description here

  • Red is the enable input
  • Green is the raw clock input
  • Blue is the enabled clock output signal

I've spaced the two upper waveforms out so you can see things a little easier.

You need a fairly strong pull-up resistor - I've used 1 kohm and I've also added 10 pF from base to ground to reduce the glitchiness on the output when the clock is disabled. You can see a little bit of it in the picture above but it is significantly bigger than this if the 10 pF is removed.

\$\endgroup\$
2
  • \$\begingroup\$ +1 yup.. again move the red disable line back 1/4 clock and the latch gets an extra unintended clock edge. \$\endgroup\$
    – Trevor_G
    Commented Mar 4, 2018 at 15:46
  • \$\begingroup\$ @Trevor_G it certainly will - synchronicity might be important so use another D type. \$\endgroup\$
    – Andy aka
    Commented Mar 4, 2018 at 15:49

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.