Using Memory values in Verilog / VHDL

Question

In Xilinx Vivado IP integrator, I want to create a custom building block. The block need to be able to access the memory space (possibly external RAM) by itself.

The target function of the block can be described in the following steps:

• I give the AXI-MM slave block two adresses:
  • 0x????_???0: a base memory address, e.g. "0x0000_ABC0".
  • 0x????_???4: an offset memory address, e.g. "0x0000_000D".
• The block should will now automatically determine the resulting memory address ("0x0000_ABCD") and fetch the data from that memory location, e.g. "0x0000_0100". This data read represents a new memory address.
• The block should now fetch data from that memory location (e.g. "0x0000_0005") and write it to AXI_MM address 0x????_???8.

p.s. I'm using 0x????_???x, as the AXI-MM base address depends on the settings in the IP configurator and on possible other connected blocks.

I haven't found any description of how a custom block should read from the memory. How should I approach this problem?

I'm using Digilent Zybo Zynq-7000 ARM/FPGA SoC Trainer Board.

Answer 1

See the Xilinx AXI Reference guide and the AMBA AXI protocol reference.

In particular, see section A3.2: "Basic read and write transactions" which details how the valid/ready handshake protocol works, and details the channel protocols for reading and writing.

You need to write an axi master which creates AXI write/read requests on the AXI bus and processes the response. You can use the DMA core to generate these requests for you, but in my experience the DMA core command interface is practically the same as the AXI address bus.

For an example AXI master, you can use Vivado to create an example AXI master IP. See this guide for details.

In short, you open create an empty vivado project and run the "Create and Package IP wizard" (page 27)

To run the Create and Package New IP wizard, from the Tools menu, select Create and Package New IP.

Then select "Create a new AXI4 Peripheral" and see page 39 for how to parameterise your new peripheral. You want to add an AXI Memory-Mapped Master interface. Once you've gone through this wizard, vivado should generate example code for your AXI peripheral and you can edit it as you please.

Answer 2

As you mention AXI: you have to write an AXI master module which outputs read and write request following the AXI protocol. Then you have to write code to accept the return data be it read return or write acknowledges.

Vivado has some basic IP to do basic reads and writes for you. If you need something beyond that you have to write it yourself. I have written a lot of AXI components. The AXI protocol seems very simple but is devilish complex to get right.