I am trying to build a transceiver for a stepped-frequency radar. As a starting point, I am trying to generate my signal on NI's AWR VSS software. I am able to generate my signal but don't know what should be the step time for changing one frequency to another.

I know that higher the step size longer the lock time. But How should I read the commercially available PLL frequency synthesizer datasheet to find out the information and can generate my stepped frequency vectors?

  • \$\begingroup\$ The solution is complex but will be greater than the LPF time constant by some multiple from the phase detector error filter. Some sweep the VCO at 1.6GHz/1us others 1 to 5 GHz with 1ns steps and gaps to get 2 cyc, 4, 6 8 ....per step \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 4 '18 at 23:29
  • \$\begingroup\$ @TonyStewart.EEsince'75. Is this question too broad in scope, or can we find a vector or bode chart somewhere? \$\endgroup\$ – Sparky256 Mar 5 '18 at 1:54
  • \$\begingroup\$ Cycle counts are inverse squared to frequency error and SNR so lock time is very non linear but best case with high jitter is slew rate dV/df * df , frequency error * dt/dV slew rate of filter * non-linear factors that degrade capture ratio and settling time. Discriminator/phase detector design is crucial. VCO anticipator may be useful \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 5 '18 at 3:43
  • \$\begingroup\$ HP had that glorious huge Freq Synth with 100 buttons on the front panel, to produce DC to 50MHz, with all step changes being phase-continuous. No PLLs used inside. \$\endgroup\$ – analogsystemsrf Mar 5 '18 at 5:02
  • \$\begingroup\$ Ahhh twas the HP5100 Freq Synth. \$\endgroup\$ – analogsystemsrf Mar 5 '18 at 5:02

Look at the components in the loop: -

enter image description here

You have a VCO that might have some small time delay or lag and it will likely be a constant delay, Then you have a frequency/phase detector that normally operates at a digital level so this can be easily simulated. The output of the F/PD goes through a low pass filter that may also have gain. This drives the VCO towards the "lock" position.

The above is a classic control system and can be easily simulated or equations formed mathematically. I've simulated one myself a few years ago to see how long it took to lock but, the devil is in the detail and, when you pick a PLL chip you have to go through the data sheet line by line to avoid missing details that could produce an error in the analysis.

I urge you to build a model in your favourite sim tool.

  • \$\begingroup\$ I am trying to use AWR VSS tool. Not sure if following a correct order of tasks. I am trying to create a stepped-signal as ideal as possible with a certain output power and it will be attenuated and many reflections will be received at the same time from different distances. And will try to figure out which type of receiving path is ideal for processing like homodyne, heterodyne or super-heterodyne etc. For now, I haven't planned to go componentwise but a system wise. Can't figure out which order I should take. It seems like a puzzle pieces :D \$\endgroup\$ – freezer Mar 6 '18 at 12:33
  • \$\begingroup\$ @freezer I have no idea what you are describing and how it relates to your question but good luck. \$\endgroup\$ – Andy aka Mar 6 '18 at 12:45
  • \$\begingroup\$ :) trying to describe my final goal and the way I am trying to do \$\endgroup\$ – freezer Mar 6 '18 at 12:59

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