# How to assert multiple properties in System Verilog

What is the most efficient way to assert multiple properties in SV ?

Example:

property x;
if(expr1)
a===b;
endproperty

property y;
if(expr2)
c===d;
endproperty


Is something like this is needed: assert (x && y)?

You can use the property and operator
assert (x and y);

For your example, there's not much difference from the logical && operator, but that operator can only be used on Boolean expressions.