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I want to understand what determines the frequency of this ring oscillator and how to lower the frequency.

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    \$\begingroup\$ Simulate variations in VDD, in temperature, number of stages and channel lengths, all these parameters contribute even if a tidy bit to oscillation frequency. If you wish for theoretical expressions, books are your source. \$\endgroup\$ – Vicente Cunha Mar 5 '18 at 17:07
  • \$\begingroup\$ Check out propagation delay; this one should run at 1/(2*(total propagation delay)). As noted, it will probably vary considerably with temperature. \$\endgroup\$ – Peter Smith Mar 5 '18 at 17:08
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    \$\begingroup\$ If you just wish to lower the frequency, I believe a lower VDD does the trick. Simulate to check this. \$\endgroup\$ – Vicente Cunha Mar 5 '18 at 17:09
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Propagation delay and charge current (Ron) * charge load capacitance Ciss * number of stages with odd number of inverters ( for self DC bias negative feedback) determines ramp time to threshold. If equal, twice the ramp time is inverse to resulting frequency. Normally RC=T is asymptotic of 1-1/e for T=64% but for CMOS it is usually 50% threshold so T is an approximation and rise time for 10~90% is Tr=0.35/f(-3db) is another approximation for a single stage.

Lowering Vdd raises Ron value and thus lowers f. Adding more C load to Ciss also lower frequency.

if Pch and Nch are same dimension then Ron is usually higher for Pch.

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Wiki says the ring oscillator frequency is set by the delays of having to charge the gate capacitance of the CMOS stages. The site also says if you increase the CMOS source voltage, the switching time will decrease so the oscillation frequency will increase. I guess this means that less gate capacitance is required to be charged before sufficient current will flow between the source and drain. You can put a cap in parallel with the gate to ground so that more capacitance is required to be charged. This could possibly decrease oscillation frequency. Lastly you could add more pairs of CMOS stages to decrease frequencty.

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