1
\$\begingroup\$

I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other placement constraints. The interface spec is 300ps maximum skew.

If the two chips are placed as close as possible, the trace lengths are between 10mm and 20mm and the delays on the different lanes are matched to 60ps.

To get a better match, I think I need to add around an extra 30mm or more space between the chips. The problem is that the lanes run quite close together; to meander them some sideways space has to be opened up first (which lengthens the outermost traces) and then the inner (shorter) traces can meander. The traces would then be matched to something like 50mm +- 2mm.

Is it worth adding the extra 30mm and meanders to get a perfect timing match, or should I keep it simple and just use the short direct connections and accept 60ps skew?

I am mostly concerned that longer traces would allow more crosstalk, and also the trace impedances / manufacturing tolerances of the board become more important. Also, doing meanders takes a bunch of time.

UPDATE There is also 50ps skew (known) due to package delays, and up to 50ps skew from the logic of the sender chip. So the trace skew budget is only 200ps, accounting for all other sources I know of.

\$\endgroup\$
  • \$\begingroup\$ Where did the 300ps spec come from? \$\endgroup\$ – EE_socal Mar 7 '18 at 22:28
  • \$\begingroup\$ @EE_socal That's from the datasheet of the receiving chip. I think it needs 300ps hold time to sample each edge, and 100ps guard band on each side of that, that leaves ~300ps possible skew out of the total ~800ps time between edges. \$\endgroup\$ – Alex I Mar 7 '18 at 22:34
  • \$\begingroup\$ Your task is the providing an adequately clean dataeye. Read up on that. Either crosstalk or skew can imperil the dataeye. \$\endgroup\$ – analogsystemsrf Mar 8 '18 at 3:29
1
\$\begingroup\$

The period of 600 MHz is 1667 ps, so 60 ps skew is very small and will not be a problem. There is no need to length match beyond this.

\$\endgroup\$
  • 1
    \$\begingroup\$ If you have DDR, the time (unit interval) is half of that, 830ps. There is also channel/clock jitter, so the timing budget might run out fairly quickly. The trade-off between the skew and crosstalk is usually judged by a solid eye diagram. \$\endgroup\$ – Ale..chenski Mar 7 '18 at 23:57
  • \$\begingroup\$ @AliChen Yup, true. Any tips short of building both versions and measuring both? Which one should I do first? What are the odds that the direct version works ok? \$\endgroup\$ – Alex I Mar 8 '18 at 1:48
  • 1
    \$\begingroup\$ @AlexI, if you use correct differential routing (keep serpentine wiggles longer than trace pair width), keep some distance between pairs (at least 3X of trace), etc etc, it should work. Don't forget to put test spots (needle-size pads) on traces, with good proximity to ground fill, to be able to fit a good differential probe to measure eye diagram, and everything will be fine... When testing, don't forget to check signal margins, at least by "wet finger test", electronics.stackexchange.com/a/279253/117785 \$\endgroup\$ – Ale..chenski Mar 8 '18 at 2:54

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.