I'm designing a board that has a LVDS 2.5V interface with 30 lanes clocked at 600MHz and DDR. This is going from one chip to another chip which could be placed right next to it, there are no other placement constraints. The interface spec is 300ps maximum skew.
If the two chips are placed as close as possible, the trace lengths are between 10mm and 20mm and the delays on the different lanes are matched to 60ps.
To get a better match, I think I need to add around an extra 30mm or more space between the chips. The problem is that the lanes run quite close together; to meander them some sideways space has to be opened up first (which lengthens the outermost traces) and then the inner (shorter) traces can meander. The traces would then be matched to something like 50mm +- 2mm.
Is it worth adding the extra 30mm and meanders to get a perfect timing match, or should I keep it simple and just use the short direct connections and accept 60ps skew?
I am mostly concerned that longer traces would allow more crosstalk, and also the trace impedances / manufacturing tolerances of the board become more important. Also, doing meanders takes a bunch of time.
UPDATE There is also 50ps skew (known) due to package delays, and up to 50ps skew from the logic of the sender chip. So the trace skew budget is only 200ps, accounting for all other sources I know of.