What are the minimum requirements to start with static timing analysis. I know usage of FPGAs and VHDL. Will that be enough? Are there any free tools for STA pls.?
closed as too broad by Andy aka, RoyC, Michel Keijzers, PeterJ, Harry Svensson Mar 10 '18 at 19:52
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Your question about "start with static timing analysis. " is some what vague.
You don't do STA. Static Timing Analysis is done by the synthesis tool(s). That tool will do a timing analysis based on the gates and try to optimize the design.
Your input in that is to define the constraints of your design. That starts with the clock frequency but if also clock uncertainty and jitter. A very important part is to define the input & output constraints of the block or design. If you know what you are doing you can do multi-cycle constraints. The language to do so differs from vendor to vendor.
After defining the constraints and running the tool you will often ask for the worst case N paths. Especially if the timing fails (constraints are not met). From that you have to decide what to do to get the design to meet timing. That is a whole different skill!
All the big FPGA vendors have a tool set which includes synthesis and STA, and can be downloaded for free. But 'learning' means you need to be confronted with a series of different designs with different timing values. That normally comes with a few years of making and breaking designs.