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What are the minimum requirements to start with static timing analysis. I know usage of FPGAs and VHDL. Will that be enough? Are there any free tools for STA pls.?

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closed as too broad by Andy aka, RoyC, Michel Keijzers, PeterJ, Harry Svensson Mar 10 '18 at 19:52

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  • \$\begingroup\$ STA is a large domain in VLSI. So much to learn before you start \$\endgroup\$ – Mitu Raj Mar 8 '18 at 15:19
  • \$\begingroup\$ OK. Thanks. Just two more queries pls.: What is the profile of an RTL engineer. Next, I know of SPICE simulations. I did Pspice simulations of schematics some time back an am interested in it (I can make small ckts. With transistors and opamps). What career path do you suggest in this line pls. (apart from PCB design). Yours sincerely \$\endgroup\$ – Arvind Gupta Mar 8 '18 at 15:38
  • \$\begingroup\$ I am just kicking off my career as RTL design engineer on FPGAs. I think your interest lies in ASIC. There are Design / Verification Jobs. RTL or Digital design, Analog Design engineer, Physical layout Design engineer, Design verification engineer, Physical verification engineer, Timing Verification Engineer, Test engineer etc \$\endgroup\$ – Mitu Raj Mar 8 '18 at 15:56
  • \$\begingroup\$ Spice simulations and all comes in ASIC design. \$\endgroup\$ – Mitu Raj Mar 8 '18 at 15:57
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Your question about "start with static timing analysis. " is some what vague.
You don't do STA. Static Timing Analysis is done by the synthesis tool(s). That tool will do a timing analysis based on the gates and try to optimize the design.

Your input in that is to define the constraints of your design. That starts with the clock frequency but if also clock uncertainty and jitter. A very important part is to define the input & output constraints of the block or design. If you know what you are doing you can do multi-cycle constraints. The language to do so differs from vendor to vendor.

After defining the constraints and running the tool you will often ask for the worst case N paths. Especially if the timing fails (constraints are not met). From that you have to decide what to do to get the design to meet timing. That is a whole different skill!

All the big FPGA vendors have a tool set which includes synthesis and STA, and can be downloaded for free. But 'learning' means you need to be confronted with a series of different designs with different timing values. That normally comes with a few years of making and breaking designs.

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  • \$\begingroup\$ OK.. thanks sir. Can you pls. point out any other options for people who know FPGAs and VHDL? I was looking to learn STA from a career option. What other topics can I look into then? Anything simple and having good market viability pls. Thanks again. \$\endgroup\$ – Arvind Gupta Mar 8 '18 at 10:17
  • \$\begingroup\$ AFAIK there is no STA career option. (I have designed ASICS for 25 years). Setting up the constraints, guiding the tools and looking at the STA results is done by synthesis & place-route people. You become one of those after multiple years as HDL designer. \$\endgroup\$ – Oldfart Mar 8 '18 at 10:23
  • \$\begingroup\$ OK. thanks again. then what other career path do you suggest for beginners with my skillset \$\endgroup\$ – Arvind Gupta Mar 8 '18 at 10:35
  • \$\begingroup\$ Well, try to get a job as FPGA/ASIC engineer. Beware that US companies are using mostly Verilog. I can't give you much of advice as I have lots of experience but no job for the last year. (Nobody wants to hire you, once you get above 55 it seems) \$\endgroup\$ – Oldfart Mar 8 '18 at 10:50
  • \$\begingroup\$ OK. Thanks. Just two more queries pls.: What is the profile of an RTL engineer. Next, I know of SPICE simulations. I did Pspice simulations of schematics some time back an am interested in it (I can make small ckts. With transistors and opamps). What career path do you suggest in this line pls. (apart from PCB design). Yours sincerely \$\endgroup\$ – Arvind Gupta Mar 8 '18 at 13:00

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