Does anyone know exact working and what will be blocks present inside the calibration module of DDR2/3 memory devices?
Any information related to calibration process of DDR2/3 SDRAM's is appreciated..
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DDR2 and DDR3 offer several new features that allow to alleviate differences in PCB channels and achieve higher communication rates. DDR3 offers driver calibration function (ODT), termination calibration (ZQ), and timing calibration.
Quick Google search shows several presentations describing these features, e.g. Micron article, and NXP article. Regarding the actual RTL implementations, the information is likely very proprietary, and this forum is not the right place to ask for details.
The SPD (serial presence detect) specification for DDR3 is JEDEC 21-C. It is 69 pages long so it would be impractical to post it here.
It is free to create a JEDEC account and to get access to many documents including 21-C.