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I want to use an ISERDESE2 to deserialize a bitstream from an ADC, but the clock of the ADC that samples the bits is discontinuous, it remains at '0' between two words sent. Is this a problem if a try to use this clock as the CLK entry of the ISERDESE2?

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  • \$\begingroup\$ Does the clock go though a PLL before driving your logic? If so, then you have a problem. If not, it might work. \$\endgroup\$ – crj11 Mar 8 '18 at 16:14
  • \$\begingroup\$ In page 31 of this document link are the figures of the outputs of the ADC. I am not sure i will need the clock to go through a PLL as i allready have i frame clock and and a clock with its transition aligned with the center of the data eye. \$\endgroup\$ – the dude Mar 12 '18 at 9:57
  • \$\begingroup\$ If you already have a continuous data-aligned frame clock, I would just ignore the TXCLK and use an 8X version of your aligned frame clock to clock the received data as if was 8 bits of data. Just ignore the unused bit. \$\endgroup\$ – crj11 Mar 12 '18 at 11:41
  • \$\begingroup\$ The problem is that my frame clock is not constant, for the first word it will stay at '1' for 4 txclk periods for the second word it will stay at '1' for 3 txclk periods etc.. it will go on alternating like that. To use a 8x version i need a pll or a mmcm right? \$\endgroup\$ – the dude Mar 12 '18 at 12:12
  • \$\begingroup\$ Yes, to generate the 8X clock you would need a PLL or MMCM. I was assuming that you are generating the INCLK to the ADC and that you can thus generate the equivalent of the TXCLK without the missing clock. Note that the ADC looks like it can generate test patterns so that you can run a calibration to use the input delay to optimally align the data to the locally generated clock. \$\endgroup\$ – crj11 Mar 12 '18 at 12:16

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