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Can someone describe the difference between the drive strength and the slew-rate preferences in Lattice FPGA?

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As its name suggest, the slewrate preference is a preference for the rate of change of the signal at the Output Pin. Though seemingly unrelated, this is coupled with the load preference (which limits the maximum output current of the pin). For small capacitive loads, the slew-rate can be achieved with any drive strength. However, as the capacitive load increases, the drive currents kicks into play. For high capacitive loads, if the drive current is too low it can be a limiting factor for attaining fast slew-rate on the pin.

To illustrate the effect of drive-strength and slew-rate I'll use examples from a project that I was involved in. I was using Lattice XP2-30E FPGA to read the data from an analog to digital converter AD9238. The problem manifested itself as wrong data being read. Measuring with digital probes revealed hold time violations. Namely, the digital probes showed larger clock jitter, with the hold time of 1.5ns (min 2ns specified by the ad converter).

Measuring with analog probe (with Yokogawa DLM2034 at 2.5GSPS) revealed serious distortion of the clock signal. The following figures illustrate the effect of slew-rate and drive strength on the clock signal.

enter image description here

As can be seen from the figure, even for the fast slew rate preference, the drive current of 4mA prevents the FPGA from attaining the desired slew-rate.

So why one shouldn't set the drive current as high as possible? If the capacitive loading of the line is large, and the FPGA is simultaneously driving multiple lines (typical application when driving a bus), the large in-rush current may cause a voltage drop on the internal supervisory circuit for poorly decoupled FPGA, causing the chip to reset. Once the desired slew-rate is attained, increasing the drive current had the negative effect as it increased overhoot in the signal.

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    \$\begingroup\$ Also a very fast rise time makes it more difficult to pass EMC regulations. To pass EMC you want a slow rise, for 'nice' signals you want a fast rise, for low power you want a slow rise. Sometimes you just can't win! \$\endgroup\$ – Oldfart Mar 9 '18 at 21:20
  • \$\begingroup\$ I spent a week tracing this problems and just wanted to post it in case someone else encounters a similar issue. I did not have problems with EMI (probably because I did not design anything that underwent EMI tests :) ) but I had problems with FPGA resetting when driving a long data bus (because of poor decoupling). \$\endgroup\$ – ercegovac Mar 9 '18 at 21:23
  • \$\begingroup\$ That's a wonderful real-life example! \$\endgroup\$ – peufeu Mar 9 '18 at 21:26
  • \$\begingroup\$ @oldfart, yes, I use the slowest slew rates that the loads on the FPGA or CPLD outputs will work reliably with. This is to reduce ringing into high-impedance loads (logic inputs) and to reduce EMI. The OP describes their situation occurring with large capacitive loads and poor decoupling. They're broader circuit problems that the FPGA or CPLD pin characteristics won't solve. Maybe hide but not solve. \$\endgroup\$ – TonyM Mar 9 '18 at 21:46
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    \$\begingroup\$ 3.3V/8mA implies a load R of 412 Ohms.. The problems in this question ignore the causes of impedance mismatch. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Mar 9 '18 at 23:55

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