Each FET has about 4" of wire in the Source, or 100 nanoHenries.
Should you be switching a current of a mere 10 amps in each FET, in 10 nanoSeconds, the inductive kick will be
Vinductor = L * dI/dT
Vinductor = 100nH * 10 amps / 10 nanoSeconds
Vinductor = 100 volts in the Source wiring.
Thus your FET gates experience 100 volt spikes.
As the gates go short, the spikes are connected to the PowerDriver IC, and destroy that IC.
USE a sheet of copper foil under your high speed (power driver) and its Surface Mount bypass caps, and the same sheet of copper foil under your several power MOSFETS. On back side, you should install some copper bus-bars to handle the 100 amps you expect to switch.
Each millimeter of FET lead (source, drain, or gate) or of wiring or thin PCB trace, is approximately 1 nanoHenry inductance; the formulas also depend on cross-section of the FET lead, or the bond wires inside the plastic, or the copper wiring (thin) I see in your photos; very wide foil has less inductance, with a natural-log dependency; GND plane over VDD plane will reduce the plane's inductive contribution by 10:1 (from memory, this is my rule of thumb for planes), but the other "wires or leads" still add ~1nanoHenry/1milliMeter.
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By the way, you at present have no means of encouraging the FETS to share those high currents. Try 0.01 ohms in the source, which is 20 squares of default thickness copper foil for the default foil weight of 1 ounce/foot^2.
You are at the mercy of how matched the FETS are, if they are at the same temperature and gate-drive voltage during the turnoff and turnoff voltage slewing.
At 10 amps per FET, that I*R drop produces 0.1 volts across the 20 squares, and 0.1 volts is plenty of signal to change the output of an analog comparator.
[I had error in prior sentence; I'd written "produces 0.2 volts across."]
Allocate one analog comparator per FET; combine the outputs with a 4-input NAND or 8-input NAND, that NAND connected to "SET" pin of a latch, and the latch output controls the "Enable" pin of your Gate Driver.
If you attempt to monitor the current in individual FETS, the intense and rapidly changing electron movement causes intensely-fast changes in the electric fields (some of which gets labeled "magnetic field") and simply measuring that 0.1 volts across 0.01 ohms may be impossible.
Suppose you make the Source-resistor 0.1 ohms. Then at 10 amps and 1 volt across the resistor, its power is one watt. Now you have a heat removal issue.
Lateral (sideways) movement of heat thru FR-4 epoxy-fiberglass is very poor, so you need a heat-removal plane under the source resistor. The default thermal resistance (spreading edge_to_edge, not face_to_face) of foil is 70 ° C per watt per square of foil.
The gate-driver IC cannot have long leads; inductive spikes/kicks will kill it.
Draw and post a schematic, with all high current and fast-changing current paths indicated; you need to think about managing the inductive spikes/kicks; both ends of any diodes need low inductance.
You have a combined mechanical / inductance / high-current / fast-edges / heat-removal / bypass-capacitor-placement challenge. Draw lots of sketches as you think about this. Memorize the speeds of the FETs and the gate-driver ICs; examine the circuits provided by the manufacturers for R+C time-constants; are the R+C components setting the edge speeds? to slow down the edges and thus reduce the inductive risks?
