I want to design a 6 layer PCB for an Allwinner H3 and DDR3, but the PCB workshop just have the stack-up shown in the image. enter image description here

With this stack-up, The calculation for striplines impedance is difficult. The width of SE signal at 50 Ohm is 18 mils. So big for DDR3 signals.

Can I layout the DDR3 SE signal with 80 or 100 Ohm instead of 50 Ohm ?

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    \$\begingroup\$ Probably not. What does the datasheet say? Also, please fix your capitalization. \$\endgroup\$ – winny Mar 12 '18 at 6:49
  • \$\begingroup\$ hi winny! thanks for your answer. in datasheet allwinner H3 don't have information for hardware design. \$\endgroup\$ – baoNG Mar 12 '18 at 7:07
  • \$\begingroup\$ If you want thinner tracks, reduce the thickness of the controlled Z layer dielectric in half or better , go for a 32 mil (0.8mm) board with even layers thicknesses \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Apr 5 '19 at 23:44

It might works or not... The only thing we can be sure of is that it should work if you use a 50 Ohm impedance. Anything else is pure speculation because it's out of specs.

Of course there is no "brick wall" (i.e.: at 50 Ohm it works but at 51 Ohm it doesn't work at all.). The transition is smooth and there is a region between the "it works" and "it doesn't works" : The infamous "It sometimes works".

Intermittent failures are part of the most difficult things to debug.

DDR3 memory buses are very sensitive to signal integrity. And you will find documents that list an intimidating set of rules one has to follow to ensure good integrity on that bus. For instance :

  • Length matching between some signals (but no all)
  • Impedance: single ended and differential
  • Grounding: Don't cross a plane boundary (GND plane or power plane)
  • Kind of decoupling caps: Use Y5V and you are stuck...
  • ...

Because debugging memory issues can be very difficult and time consuming, I strongly suggest that you try to follow exactly all the recommendations and guidelines. It's difficult enough to ensure a reliable design when trying to follow the rules...

If you PCB shop cannot provide a suitable stack-up, find another one that can.

  • \$\begingroup\$ Thank you very much! The answer is very detailed, i understand and maybe i will find another PCB shop. :) \$\endgroup\$ – baoNG Mar 12 '18 at 8:19

With signal routing on top and bottom layer, and GND on layer 2 and 5, you should have to trouble reaching 50 ohm SE impedance with the 0.11mm prepreg and about ~5mil traces.


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