I am trying to simulate an ISERDESE2 component with VIVADO Networking mode SDR 8 bits wide. I emulate the behaviour of the ADC: CLK and CLKDIV are phase aligned, CLK has its transitions aligned with the center of the data eye. On the D port of the ISERDESE2 i always send the same word "10101011" The words that i send for deserialization are equal to "10101011" but in the outputs the result is "10111010".

The result is shifted, i assume i need to use the bitslip signal to barrel shift the result 3 times to get the right word.

But in that case i don't understand the use of CLKDIV it was suppose to be useful to determinate the beggininng and the end of the words, it doesn't seem to be the case.

And when i will use an ADC and try to deserialize the bitstream how can i know how many bitslips will be required as i don't know the content of the words sent by the ADC?

Thank you for your helpenter image description here


As it stands CLKDIV is aligned with CLK. If you delay it by 1/2 CLK, it would be aligned with the data. If you put the delayed version into an additional ISERDES2 input and clock it along with the data, you could use the resulting pattern to determine the data phase with respect to CLKDIV. You would keep slipping bits until the deserialized delayed CLKDIV is aligned such that you know the data is also aligned. The actual aligned pattern depends on the relative phase shift between your delayed CLKDIV and the data, but the pattern would be a rotated version of 11110000.

  • \$\begingroup\$ Thank you, so the for the second iserdese2 i will use the delayed version of CLKDIV and use it as an input for the D port, but which signal will i use for the CLKDIV port? Is this what they are doing in Figure 6? xilinx.com/support/documentation/application_notes/… \$\endgroup\$ – the dude Mar 12 '18 at 17:51
  • \$\begingroup\$ All of the ISERDES2s should be connected the same except for their external inputs. That way they will all shift the same when you do the bitslip. \$\endgroup\$ – crj11 Mar 12 '18 at 17:53
  • \$\begingroup\$ As for figure 6, I'm not sure. \$\endgroup\$ – crj11 Mar 12 '18 at 17:55
  • \$\begingroup\$ what do you mean by external inputs? (CLK, CLKDIV, D, RST, CE1, CE2..) \$\endgroup\$ – the dude Mar 12 '18 at 17:56
  • \$\begingroup\$ By external inputs I mean the I/O pins on the FPGA, which in the case are the data inputs and the shifted DIVCLK input. \$\endgroup\$ – crj11 Mar 12 '18 at 17:56

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