I am trying to simulate an ISERDESE2 component with VIVADO Networking mode SDR 8 bits wide. I emulate the behaviour of the ADC: CLK and CLKDIV are phase aligned, CLK has its transitions aligned with the center of the data eye. On the D port of the ISERDESE2 i always send the same word "10101011" The words that i send for deserialization are equal to "10101011" but in the outputs the result is "10111010".
The result is shifted, i assume i need to use the bitslip signal to barrel shift the result 3 times to get the right word.
But in that case i don't understand the use of CLKDIV it was suppose to be useful to determinate the beggininng and the end of the words, it doesn't seem to be the case.
And when i will use an ADC and try to deserialize the bitstream how can i know how many bitslips will be required as i don't know the content of the words sent by the ADC?