I am looking for the easiest solution to

  • synthesize 1.6 - 2.4 GHz (qudrature)
  • in steps of 4 MHz
  • settle within 10-50ns
  • precise timing control when to switch frequency (e.g., at rising edge of an external signal, frequency should be updated)
  • total integrated phase noise (jitter) between 1 MHz and infinity < 400fs rms
  • Cost and power is irrelevant (in a meaningful range) to the extend that they do not add significant complexity or add other problems (like thermal issues)

In considered the following solutions:

  1. PLL. Settling time cannot be met
  2. DDS: The best I found is the AD9914/AD9915 with fclk=3.5 GHz (i.e., fmax=1.75 GHz)
  3. DAC/RFDAC: There are many options (AD9161 at 12 Gsps etc). However, they require that the digital signal is generated externally and high-speed samples pumped into the DAC. A high-end FPGA could implement DDS logic and spit out the samples. However, this has tremendous complexity. Besides, these high-speed RFDACs are 200 ball BGAs requiring 12 PCB layers, serdes and a careful design that would take many months to complete
  4. DDS+Mixer. Let's take the AD9910 as an example followed by a mixer with fc=2 GHz. The issue is that the mixer needs to be an image rejection mixer and hence I need two DACs for each I and Q channel - a total of 4 DDS and 2 Quadrature!
  5. DDS+I/Q Modulator: Basically the same as 4 but the output of the DDS systems is shared between the modulators (2xDDS, 2xIQ Modulators). This would be "ok" but it cannot control the phase difference between the I and Q branches for I/Q compensation.

Is there anything I forget? The AD9956 is a 400 MHz DDS system but claims:

The AD9956 uses advanced DDS technology, an internal high speed, high performance DAC, and an advanced phase frequency detector/charge pump combination, which, when used with an external VCO, enables the synthesis of digitally programmable, frequency-agile analog output sinusoidal wave- forms up to 2.7 GHz

Two application circuits are given in the datasheet:

enter image description here enter image description here

but I do not understand them. What would be the switching time from, say 1.6 to 2.4 GHz for these?

Is there any other hybrid DDS+PLL or DDS+Mixer system?

  • 2
    \$\begingroup\$ DDS plus frequency doubler? Not sure what challenges you'd run into trying to cover near a full octave with this scheme, or where to get a doubler for this frequency band. \$\endgroup\$
    – The Photon
    Commented Mar 14, 2018 at 5:16
  • \$\begingroup\$ I think some mixture of DDS + mixers and multipliers can do this. I have seen something similar done, but I wasn't involved in the RF design. I did design a PCB with FPGA and 2 DDS's on it. \$\endgroup\$
    – user57037
    Commented Mar 14, 2018 at 5:25
  • \$\begingroup\$ A bit of googling found some possibly appropriate doublers at Macom. \$\endgroup\$
    – The Photon
    Commented Mar 14, 2018 at 5:27
  • 1
    \$\begingroup\$ Couldn't you generate a constant 1.6 GHz somehow. Then mix in the output of your DDS? The DDS would instantly jump to any frequency between 0 and 800 MHz to produce an output of 1.6 to 2.4 GHz. Then you only need a high pass on the mixer output. You can have two separate channels, one for inphase and one for quadrature. The phase difference can be generated by the DDS's \$\endgroup\$
    – user57037
    Commented Mar 14, 2018 at 5:36
  • 1
    \$\begingroup\$ you tell us something about the settling time, but how much time do you have between two frequency switches? Can you hold a second LO "on the ready" and just switch over? \$\endgroup\$ Commented Mar 14, 2018 at 14:21

5 Answers 5


One option is using a DDS that can reach 1.2 GHz, with a frequency doubler.

Doublers are essentially just some nonlinear circuit to produce harmonics with some filtering to pick out the preferred 2nd harmonic at the output, so they don't require any lock-in time when changing frequency (aside from that implied by the bandwidth of the selection filter).

Doublers tend to allow at least a bit of the input frequency (perhaps 20 dB or so below the 2nd-harmonic output), and also its 3rd harmonic, through to the output, so some careful filtering, or even an adjustable filter, might be required if you need a very pure output frequency.

Doublers also tend to be a bit fussy about the power level at the input, and produce an output attenuated from the input level, so you may need some additional amplification and/or attenuation to get the scheme working well.

Two application circuits are given in the [AD9566] datasheet... What would be the switching time from, say 1.6 to 2.4 GHz for these?

Those are both essentially PLL schemes. The switching time will be limited by the bandwidth of the loop filter. I'd expect it to be difficult to get it below a several 10's of ns. Although 50 ns doesn't seem totally out of the question if the loop bandwidth can be as high as 20 MHz. (This also applies to your proposal of a straight PLL solution)


I would concentrate on the VCO and try to find a design that has a reliable change in frequency per volt. Something that can almost be run "open-loop".

This is a priority because my suggestion would be to use a PLL but with feedforward to get you the speed (and distance to the next hop) then the PLL loop would tweak the final few MHz. So how accurate and in what time do you want it to be?

You can get quadrature outputs using two resistors, an inductor and a capacitor across a vast range of frequencies but with some amplitude variations.


One option would be DDS in the lower frequency range (e.g. AD9956) and double conversion with a LO switchable in 200MHz or 400MHz steps.

While double conversion may look more complex, it means you can avoid I-Q mixing, because it allows you to place the image well out of the band of interest.

For example, if DDS can comfortably cover 100-300MHz, then a simple conversion with a LO of 500MHz would give an upper sideband of 600-800MHz and an easily rejected lower sideband.

Then another simple conversion with four spot frequencies of 1.0, 1.2, 1.4 or 1.6GHz would cover the required range. (The last LO reaches the bottom of the band here, so the mixer should be balanced for low LO leakage)

Variations are obviously possible; if DDS can easily cover a 300MHz low band range, then only 3 spot frequencies would be required. It may be possible to make the 2nd LO spot frequencies harmonics of the first LO. And so on.


You can use a AWG + DDS + Marki IQ-1545 IQ Mixer if you need to have baseband modulation. (Else a DDS can have good results on CW frequency hopping). There are always IQ mismatch in component. You need to measure it and perform calibration either by predistortion or equalization. You cannot escape that if you want good performance.

The calibration can be perform either at the IQ files, or for high quality AWG, one can control the phase, time and amplitude differences in between I and Q.

keysight UXG as DDS LO can hit 50ns hopping time under certain condition.

The disadvantage of using PLL based technology is settling time, and this is as high as 1 ms in instrument grade product (component grade product may be worse). Hence PLL technology is not suitable for agile signal.


Referring to your list of requirements, synthesizing up to 2.4 GHz (quadrature) and settling within 10-50 ns are probably the main parameters limiting your choices of synthesis method. It rules out PLL only; though PLL could be used in a hybrid design. The intended end-use can also assist in choosing one integrated circuit over another.

There are a number of different categories of frequency hopping:

Depending upon which types of hop is needed it may be possible to find an integrated circuit specifically for the purpose, relying on a mass production device over something with additional unneeded features.

The manufacturers of the integrated circuits have a number of helpful training videos available:

DAC under consideration:

  • The Analog Devices (AD) AD9915 that you were considering is a good choice, it has five modes of operation: • Single tone • Profile modulation • Digital ramp modulation (linear sweep) • Parallel data port modulation • Programmable modulus mode

Suggested DACs:

The DACs that I suggest below are alternatives to the AD9914/AD9915 that you were looking at.

  • If you are willing to multiply or upconvert the output there are DACs that have a lower maximum output frequency but much greater flexibility. The AD AD9102 is a low power, 14-Bit, 180 MSPS, DAC and Waveform Generator featuring: • Sawtooth generator output • Pseudorandom sequence generator output • DC constant generator output • Pulsed, phase shifted DDS sine wave output • RAM output • Pulsed, phase shifted DDS sine wave output amplitude, modulated by RAM output • Continuous waveforms • Periodic pulse train waveforms that repeat indefinitely • Periodic pulse train waveforms that repeat a finite number of times

  • The Texas Instruments (TI) DAC38RF83 is a dual-channel differential output, 14-Bit, 9-GSPS, RF-sampling DAC With JESD204B interface and on-chip PLL, allowing an input data rate of 1.25 GSPS complex per channel. It also features 6-24x interpolation and 4 independent NCOs with 48-Bit resolution.

  • The TI DAC39J82 Dual-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface features: • 1x-16x Interpolation • Independent Complex Mixers with 48-bit NCO/ or ±n×Fs/8 • Wideband Digital Quadrature Modulator reconstruction filters • Sinx/x Correction Filters • Fractional Sample Group Delay Correction

  • Don't forgot the lesser known manufacturers:

Additional Information:

The frequency produced can maintain phase in two different ways:

  • Each frequency can maintain phase coherency to itself (upon switching back to the frequency it will be phase coherent), that produces a much wider bandwidth and possibly unwanted spurious content but allows each channel to resynchronize quicker when it is switched to.

    A use case for that would be one transmitter and multiple receivers, such as a cell tower, each receiver doesn't want to have to resynchronize when the transmitter comes back to it's channel.

  • The output frequency produced can transition smoothly and continuously, producing no spurious content and maintaining the narrowest possible bandwidth. A frequency change (of the carrier) must be differentiated from a temporary phase or frequency change, as would occur from modulation.

    A use case for that would be one or more transmitters (such as occurs with single channel simucasting, or Project 25 trunking simulcast) communicating with one or more receivers on a spread spectrum channel (not used in P25, but used by other protocols). Maintaining as small a bandwidth as possible while switching 100's of thousands of times per second allows the transmitted signal to sit beneath the noise floor.

Figure 1 - Example of Phase Coherent Frequency Hopping

Figure 2 - Example of Phase Continuous Frequency Hopping Image source: "Evaluating the frequency hopping capability of the AFE74xx"

A general approximation relating rise time to the spectral bandwidth is:

$$BW \approx \frac{0.5}{t_r}$$ Examples: 100 ns rise time, peak to peak = 5 MHz, 10 ns = 50 MHz, 1 ns = 500 MHz.

Of course a pure sine wave won't have that bandwidth, but rapidly switching from one frequency to another increases the bandwidth momentarily or filtering smooths the transition time and affects the rate change.

"The clock distribution is usually generated by an instrument during characterization, allowing a wide range of reference frequencies. The clock distribution circuit serves to buffer the incoming reference and sets up the appropriate tirning between the digital part of the DDS and the BAC. The important specifications here are the DAC's input data setup and hold times. Even a slight violation of these specifications can cause an increase in glitch impulse if the latch is transparent, or capture of erroneous data if the latch is edge triggered.".

Source: "Choosing DACs for Direct Digital Synthesis" by David Buchanan

See also: Carson's bandwidth rule

$$\text{CBR}=2(\Delta f+f_{m})$$       where:

      \$\text{CBR}\$ is the bandwidth requirement;
      \$\Delta f\$ is the peak frequency deviation;
      \$f_{m}\$ is the highest frequency in the modulating signal.

The "glitch impulse" and clock feedthrough are important, as well as the "settling time" which depends upon a number of hard to predict and calculate factors, but it will be much less than what is incurred by using a PLL (assuming proper design).

DDS Glitch Impulse


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