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FIFO ERROR[![enter image description here][2]][2]I am trying to simulate a FIFO generated by the IP Catalog.

I chose for the FIFO implementation an independant clock BRAM with empty full almost empty almost full flags.

It is 7 bits wide and 16 bits deep.

I don't understand when I deassert the reset all the flags remain at '1' it means that FIFO is empty and full at the same time?

Then I assert the write enable to '1' and I write a couple of times the word '03' in the FIFO but it takes me 11 read clock cycle to finally read the word '03' and it reads it only twice, but I wrote the word more than two times.

And during the write and reading the empty and full flags don't make sense to meempty flag

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  • \$\begingroup\$ "IP Catalog": What software are we talking about? BRAM: Um, which device are we talking about? \$\endgroup\$ – Marcus Müller Mar 14 '18 at 12:08
  • \$\begingroup\$ Your second image is missing, by the way. \$\endgroup\$ – Marcus Müller Mar 14 '18 at 12:09
  • \$\begingroup\$ First make sure your input signals are defined from the beginning. (tb_wr_en & tb_rd_en). Then I might have another look. \$\endgroup\$ – Oldfart Mar 14 '18 at 12:18
  • \$\begingroup\$ Okay i will try that \$\endgroup\$ – the dude Mar 14 '18 at 12:21
  • \$\begingroup\$ @oldfart done, maybe it is because the reset is asynchronous? \$\endgroup\$ – the dude Mar 14 '18 at 12:28
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Looking at the waveform the FIFO has a fall-trough time of ~14 clocks. The behavior of the status flags after a reset seems such that it gives a 'safe' state (See below). For details you have to ask Xilinx about that. I am only worried about the 'X' from the tb_wr_rst_busy.

Further I advice you not to write to the FIFO when it claims to be full. Your three times 0x03 coming out corresponds with your write enable active at the same time as the full flag is low.

Same for the read: do not read when it claims to be empty.

This is also the likely explanation for the status flags after a reset: On the write side it claims to be full, on the read side it claims to be empty. This should prevent your logic from 'doing' anything with the FIFO until the reset has completed.

And yes, a FIFO with independent read and write clocks (Asynchronous FIFO) is bound to have large latency between input and output.

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  • \$\begingroup\$ Does the fall through time depends on the depth of the FIFO? when you say 14 times cycles you are talking about the read clock cycles right? Thanks i understand now that the reset takes some time and i started asserting enables before the end of the reset. \$\endgroup\$ – the dude Mar 14 '18 at 13:02
  • \$\begingroup\$ It depends on the way the FIFO has been build. Most of the time is used for transferring data safely between the clock domains. For a very deep and fast FIFO they might need more clock cycles to safely convert from binary to gray code and back. \$\endgroup\$ – Oldfart Mar 14 '18 at 13:10
  • \$\begingroup\$ I see something weird in my simulation, I reset the FIFO and wait till the full flag shows '0' then i write 3 words, i wait till the empty flag shows '0' then i read one word, then i second and the empty flag shows '1' i only read 2 words out of the 3 written words and the FIFO is allready empty? I edited the image of the simulation : FIFO ERROR \$\endgroup\$ – the dude Mar 14 '18 at 16:05
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    \$\begingroup\$ It's difficult to line up the clock edge without a cursor but it looks to me the FIFO is working as it should. Four values in, four values out. I can't check the intermediate values but the last one in & out is the 0x78. Beware: your rd_en is still be asserted when the FIFO is empty. This FIFO seems to ignore it, but not all FIFOs do! \$\endgroup\$ – Oldfart Mar 14 '18 at 18:11
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    \$\begingroup\$ The empty flag is low again a short time later. This sort of behavior is normal if you cross clock domains. \$\endgroup\$ – Oldfart Mar 15 '18 at 14:21

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