2
\$\begingroup\$

I am wondering if such a thing exists, as I could really use one to hookup to a SoC I am designing a board around, as it would allow me to take like a pci-e tv controller, pci-e ethernet card, pci-e GPU. It should take in some signal a mobile SoC can provide, like SPI, USB, or straight driving it from gpios(probably slow) and then outpu a pci-e x1 lane(s) or more. Does somebody know of such a thing, that is reasonably priced = < $12?

Thanks

\$\endgroup\$
  • \$\begingroup\$ Not gonna happen. Use a more capable SoC. \$\endgroup\$ – pericynthion Mar 14 '18 at 21:09
  • 1
    \$\begingroup\$ Why is that "not gonna happen" I know they exist, just can't find them anymore. \$\endgroup\$ – appmaker1358 Mar 14 '18 at 21:10
  • 1
    \$\begingroup\$ I would be surprised if it existed. It would be a bit like trying to find a hook to append a big travel trailer to a bicycle. You should look for a cheap single board computer with pci-e instead. \$\endgroup\$ – dim Mar 14 '18 at 21:12
  • 1
    \$\begingroup\$ Thats the thing, I do NOT want to use singleboard computers. I want to design it myself, otherwise, what would be the fun of it? \$\endgroup\$ – appmaker1358 Mar 14 '18 at 21:15
  • \$\begingroup\$ I hope you have documentation for that GPU, you aren't trying to use a desktop GPU for example. \$\endgroup\$ – immibis Mar 14 '18 at 21:50
1
\$\begingroup\$

Usually the PCIe root complex is a part of the SoC. If PCIe is needed you just select an SoC that has it built-in. Example: i.MX6, Sitara.

It could of course be designed in an FPGA and connected by SPI or anything to the SoC, but that defeats the main point of PCIe, which is high-bandwidth applications. Having SPI on the host side could work but would make in unbearably slow.

\$\endgroup\$
  • 1
    \$\begingroup\$ Aside from being unbearably slow such a system would have the problem of needing a rewrite for the drivers. Drivers for PCIe perhipherals expect the perhipheral to be memory mapped (or in some cases IO mapped on CPUs that support it) and they expect the perhiperal to be able to do bus master DMA to/from main memory. \$\endgroup\$ – Peter Green Mar 14 '18 at 21:19
  • \$\begingroup\$ @PeterGreen, actually the USB3.0 bandwidth kind-of matches the one-lane PCIe-1X. However the rest of your remark is spot on, there is no way to map/reverse the USB pipe/endpoint framework back into PCIe bus-mastering architecture. \$\endgroup\$ – Ale..chenski Mar 15 '18 at 3:18

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.