# MOS Cascode Bias Quesiton I'm confused about how this circuit operates. Here's what I know. Vbias sets transistor Q2 in saturation. The input small-signal vi is applied at the gate of Q1 along with an appropriate DC voltage also at gate of Q1 that isn't shown but is applied when cascode amplifiers are implemented.

Now, if both of these transistors are set in saturation by DC voltages, what's the point of current source I?

• For a sec, I thought that was my mouse cursor LOL... Anyways, the $I$ in these textbook figures provide a confirmation these devices are in saturation and to give you an easy equation to calculate particular parameters in the circuit. (Next time, use the snipping tool instead of the Print Screen key) – KingDuken Mar 14 '18 at 21:12
• Why do you think they are in saturation? I haven't studied this circuit but it looks like both are operating in their linear regions – Loganf Mar 14 '18 at 21:30
• @Loganf It's a Casocde Amplifier. For amplifiers that I have met so far, MOSFETs are always in saturation. – AlfroJang80 Mar 14 '18 at 22:12
• @KingDuken so there isn't really a current source there? – AlfroJang80 Mar 14 '18 at 22:12
• @AlfroJang80 I mean, there's always some current provided by $V_{DD}$ yes. But for the sake of the textbook, it usually gives you that reference current anyways. But to control the amount of current that you need, you'll have to use a current mirror to provide the amount of current $I$ may have... That's what (most) current sources are. – KingDuken Mar 14 '18 at 22:16

Essentially, what's happening in this circuit is something like this:

The bias on the gate of Q2 is holding its source roughly at a constant voltage. Because this is also the drain of Q1, then the Vds of Q1 doesn't change much and it is in the saturation mode. But because the gate of Q1 is varying, the current is also varying.

But of course the current through Q1 is also through Q2, which has a roughly fixed gate voltage, so that variation appears as a changing Vds for Q2. Hence you get your voltage amplifier. (Q2 is not in saturation mode)

There is negative feedback between the Q1 drain voltage and the gate of Q2 so that if Q2s Vgs gets too big, the current drawn through Q1 pushes it towards linear operation where it will start to increase Vds and reduce Q2s gate voltage.

To see all this, have a look at this graph: