I have a question on metastability and clock crossing domain. I need to deserialize a bitstream out of an ADC. TXCLK, TXOUT1, INCLK are the outputs of the ADC. So the idea was to register the DATA TXOUT1 on a shift register clocked by TXCLK then capture the parralelized data on every rising edge of INCLK and then write the captured data on an asynchronous FIFO (two independent clocks). My problem is that the module SHIFT REGISTER is clocked on TXCLK and the module CAPTURE is clocked on INCLK. INCLK is way slower than TXCLK and i don't know if i will face metastability problems crossing from a fast clock domain (TXCLK) to a slow clock domain (INCLK)
You say that TXCLK and INCLK both come from the ADC, so they shouldn't be asynchronous with respect to each other. They should be derived from a common internal source, which means they really belong to the same clock domain, and there's no reason to expect any issues with metastability. See whether the ADC datasheet (which you haven't provided) confirms this.
You do need to be careful not to introduce excessive skew between the two clocks, either in the PCB wiring between the two devices, or inside the FPGA.