I need 100MHz clock frequency to implement my HDL design on an FPGA. Is it better to use an FPGA board with 100MHz crystal oscillator or use PLL to increase the frequency? What are the advantages and disadvantages of them?
closed as off-topic by Andy aka, Michel Keijzers, Finbarr, Voltage Spike, Dmitry Grigoryev Mar 19 '18 at 14:14
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As long as you are able to generate the frequency you want from the available on board clock and PLL, it is better to use the PLL.
One of the main purposes of a PLL in an FPGA is to generate clocks of a desired frequency based on the available reference frequency oscillator. Using the PLL also allows you to generate different clock phases and frequencies that are guaranteed to have a fixed phase relationship, which is very useful in many designs.
In many cases, timing closure is easier with an internally generated PLL clock than a global clock input. Because of this it is not unusual to use a PLL to generate the exact same frequency as the input clock.
Generally, a PLL would be the cheaper option, as it would require a lower-frequency crystal to generate the synthesizer clock.