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I have one of these common digital phase lock loops which compares the frequency and phase with a VCO (local oscillator) via a phase lock loop. I failed to understand why Figure (2) (A) and Figure (2)(B) seems to follow very different logic despite they are the same device.

How does one know what OUT look like given the form of signal from +IN and -IN?

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  • \$\begingroup\$ Did you consider in your analysis that the two D FFs are positive edge triggered? \$\endgroup\$ – AlmostDone Mar 15 '18 at 17:19
  • \$\begingroup\$ What's your question? If it's about how a FPD works then there are plenty of sites on the net that explain this. Do some research. \$\endgroup\$ – Andy aka Mar 15 '18 at 17:19
  • \$\begingroup\$ sit down with a long piece of paper, and some time, and work your way through the transitions in the diagrams. Or, get a copy of LTSPICE (free), set up the waveforms and the circuit and watch them happen. There's no substitute for seeing it yourself. \$\endgroup\$ – Neil_UK Mar 15 '18 at 17:43
  • \$\begingroup\$ Sorry, i'm not an engineering student, i ask because im not familiar to this subject. \$\endgroup\$ – el psy Congroo Mar 16 '18 at 16:39
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2(C) shows the PFD with constant waveform time-delay, where the +IN always occurs some small time before the -IN edge. The Out waveform should be labeled "CP out", because that is the SUM of the two internal waveforms, the UP and the Down.

Let's back up a bit, and consider how this 2-FlipFlop PFD behaves (some PFDs have more internal logic, to achieve yet more useful behavior, but I'll let you research that). This simple PFD (and an EXOR gate is a PhaseDetector but not a Frequency Detector) pushes UP on the VCO if the Fref_input (re-label the +IN as Fref) rising edge occurs first.

And if the other input -In (re-label it as Fvar, from the voltage-controlled oscillator) rising edge occurs first, this PFD pushed DOWN on the VCO.

Here is a better drawing of the same logic diagram.

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ @Dave Tweed: It is still quite confusing, I just need to understand figure 2A, let's start from the beginning, firstly, it was triggered on positive edge of +IN,(UP=1,DOWN=0) so out is +1, ignoring negative edge so the OUT maintain its +1 value, next we triggered now on -IN (+1), with its positive edge before the positive edge of +IN (0), so we have (01) = -1, following the logic table, and at some point, i have the case (11) so, why is the OUT = 1 in this case? \$\endgroup\$ – el psy Congroo Mar 16 '18 at 16:38
  • \$\begingroup\$ No, when the first rising edge on -IN occurs, you first have (UP=1, DOWN=1) until the DELAY finishes, after which you have (UP=0, DOWN=0). The table doesn't show it, but OUT=0 for both of these cases, because for the 11 case, the two current sources cancel each other out. This is why it shows OUT going to 0 until the next rising edge of +IN, at which point, the whole process starts over. \$\endgroup\$ – Dave Tweed Mar 16 '18 at 17:47
  • \$\begingroup\$ @Dave Tweed but the first rising edge on -IN occurs, the +IN edge is zero. Don't you first have -IN (DOWN = 1) and +IN (UP = 0)? and doesn't this mean you have charge -1? but the OUT shows zero. \$\endgroup\$ – el psy Congroo Mar 17 '18 at 16:09
  • \$\begingroup\$ No. The fact that +IN has gone to zero does not mean that UP has also gone to zero. It remains at 1. That's how a DFF wired in this manner works -- the output goes high on the first rising edge after a reset, and remains high until the next reset. \$\endgroup\$ – Dave Tweed Mar 17 '18 at 16:34
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why Figure (2) (A) and Figure (2)(B) seems to follow very different logic despite they are the same device.

That phase-frequency detector is a hybrid of two designs, one of which has good phase-synchronizing properties (the XOR type) and the other of which has good frequency-synchronizing properties (the counter type). A look at a simpler PLL design CD4046might be a good start: both XOR and counter are available separately in that primitive chip, but each has drawbacks.

The XOR-type phase detector generates a signal which is most sensitive at a bias that corresponds to 90 degree phase shift between the two input signals. XOR detectors don't, however, deal gracefully with large frequency mismatch. XOR behavior is illustrated in figure 2B of the PFD hybrid datasheet. The other behavior is counter-type frequency detector, which is most sensitive to frequency differences (and is susceptible to noise from multiple-trigger events). It is that kind of detection illustrated in figure 2C.

How does one know what OUT look like given the form of signal from +IN and -IN?

That was the point of the illustrations 2A, 2B, 2C; to show the behaviors in several cases. 2B shows XOR-like phase detection, and 2C shows counter-like frequency detection, with some dependence on the phase shift. Figure 2A illustrates that a large frequency mismatch generates a large correction signal.

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  • \$\begingroup\$ What are you talking about?!? There is no XOR here. All three diagrams show the behavior of the "counter-like" detector for various situations. \$\endgroup\$ – Dave Tweed Mar 16 '18 at 12:06
  • \$\begingroup\$ @DaveTweed Examine figure 2B: the phase-lead causes rising-edge pulses, where an XOR would cause both rising-edge and falling-edge pulses. The detection is half the amplitude of an XOR phase result, but entirely similar in its phase sensitivity. Similarity here is in the logic-table, not the mechanism. \$\endgroup\$ – Whit3rd Mar 16 '18 at 21:51
  • \$\begingroup\$ So why does your answer state, "2B shows XOR-like phase detection" when it clearly does not, for the reason you just stated. This whole mess is just going to confuse the OP. \$\endgroup\$ – Dave Tweed Mar 17 '18 at 0:44
  • \$\begingroup\$ @DaveTweed : I called it XOR-like because that shows no frequency detection, only phase detection, i.e. conversion of phase error to an output signal. Just as an XOR would. \$\endgroup\$ – Whit3rd Mar 17 '18 at 1:02

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