why Figure (2) (A) and Figure (2)(B) seems to follow very different logic despite they are the same device.
That phase-frequency detector is a hybrid of two designs, one
of which has good phase-synchronizing properties (the XOR type)
and the other of which has good frequency-synchronizing properties
(the counter type). A look at a simpler PLL design CD4046might
be a good start: both XOR and counter are available separately in that
primitive chip, but each has drawbacks.
The XOR-type phase detector generates a signal which is most sensitive at a bias that corresponds to 90 degree phase shift between the two input signals. XOR detectors don't, however, deal gracefully with large frequency mismatch. XOR behavior is illustrated in figure 2B of the PFD hybrid datasheet. The other behavior is counter-type frequency detector, which is most sensitive to frequency differences (and is susceptible to noise from multiple-trigger events). It is that kind of detection illustrated in figure 2C.
How does one know what OUT look like given the form of signal from +IN and -IN?
That was the point of the illustrations 2A, 2B, 2C; to show
the behaviors in several cases. 2B shows XOR-like phase detection,
and 2C shows counter-like frequency detection, with some dependence on the phase shift. Figure 2A
illustrates that a large frequency mismatch generates a large