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I am having problems with my verilog test bench. Every time I try to run it, I get the error in the title above for my four switch registers. I have searched this question numerous times but I cannot find any answer that solves my problem. Thanks

// Module
module proj1 (A,B,C,D,a,b,c,d,e,f,g);

    input A,B,C,D;
    output a,b,c,d,e,f,g;
    wire w1,w2,w3;

    // For a/d/e/f/g outputs
    and(a , d , e , f , g , A , 1);

    // For a/d/e
    and(a , d , f , ~B , ~D);

    // For a
    and(a , C , 1);
    and(a , B , D);

    // For d
    xor(d , C , D);
    and(d , ~A , ~B);

    //For e/f   
    and(e , f , ~D , ~C);
    and(e , f , ~D , B);


    // For f/g
    and(f , g , B , ~C);

    // For f is above in the section For e/f
    and(g , C , ~D);
    and(g , C , ~A , ~B);




    // For b/c outputs
    and(b , c , ~B , ~C , ~D);

    // For b
    xnor(w2 , C , D);
    or(w3 , ~B , w2);
    and(b , w3 , ~A);

    // For c
    // w1 is the output of the below or expression so it can be used in the
    // following and expression
    or(w1 , ~C , D , B);
    and(c , ~A , w1);

endmodule 



// Test bench

module testbench4proj1();

    reg [3:0] switches;
    wire [6:0] leds;

    proj1 pr1(leds[6] ,leds[5] ,leds[4] ,leds[3] ,leds[2] ,leds[1] , leds[0], switches[3] , switches[2] , switches[1] , switches[0]);

        initial
            begin
                switches = 0000;
                $display("numbers:n     switches=ABCD   leds=abcdefg\n");
                #80 $finish;
            end

        always
            begin
                #10 $display("%h    " , switches , "%b  " , switches ,"     ", leds);
                switches = switches + 0001;
            end

endmodule
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  • \$\begingroup\$ Try specifying switches and then leds in your testbench: proj1 pr1(switches[3]..... ,leds[6].....) \$\endgroup\$ – Nazar Mar 15 '18 at 20:09
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You have an error in connecting up to your proj1 module. You should not try to drive your module output ports from your testbench. The following will drive your inputs from the testbench:

proj1 pr1(switches[3] , switches[2] , switches[1] , switches[0], leds[6] ,leds[5] ,leds[4] ,leds[3] ,leds[2] ,leds[1] , leds[0]);

It is a better practice to use connection-by-name instead of connection-by-order. Refer to the free IEEE Std 1800-2012, 23.3.2.2 Connecting module instance ports by name.

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