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after synthesis in xilinx vivado, I am getting the WARNING:

[Synth 8-5788] Register next_state_reg in module example_code is has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code.

why am I getting this warning and how to solve it without changing the logic in the below code sample ?

always @(posedge clk or posedge rst) 
begin
    if(rst)
        state <= a;
    else
        state <= next_state;
end
always @(posedge clk or posedge rst)
begin
    if(rst)begin
        count = 1;
        wt_refresh = 0;
    end

    else begin
        case(state)
            a: begin                              
                wt_refresh = 0;
                if(in_put)
                   count = count;

                else if(count < hold*30)   
                   count = count+1;          

                else begin
                   count = 1;
                   next_state = b;
                   wt_refresh = 1;                                              
                end     
               end

            b: begin                                
                wt_refresh = 0;
                if(in_put)begin
                    count = 1;
                    next_state = a;
                    wt_refresh = 1;                                  
                end

                else begin
                    if(count != 20)       
                        count = count+1;                                 

                    else begin
                        count = 1;
                        next_state = c;
                        wt_refresh = 1;                            
                    end    
                end
               end

            c: begin                            
                wt_refresh = 0;
                if(in_put)
                    count = count;

                else if(count < hold*15)                        
                    count = count+1;                        

                else begin
                   count = 1;
                   next_state = d;
                   wt_refresh = 1;                       
                end 
               end

            d: begin                            
                wt_refresh = 0;
                if(in_put)begin
                    count = 1;
                    next_state = a;
                    wt_refresh = 1;                     
                end

                else begin
                    if(count != 20)     
                        count = count+1;                            

                    else begin
                        count = 1;
                        next_state = e;
                        wt_refresh = 1;
                    end  
                end
               end

            e: begin                            
                wt_refresh = 0;
                if(in_put)begin
                    count = 1;
                    next_state = a;
                    wt_refresh = 1;                     
                end

                else
                    next_state = e;

              end   
        endcase
    end
  end
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  • \$\begingroup\$ It looks like you're trying to do a two always block state machine, but both are sequential. I would recommend converting the second always block to combinatorial and moving the sequential parts to the first always block. \$\endgroup\$ – alex.forencich Jul 22 '18 at 18:59
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I have seen that error many times and I find it very annoying and very misleading.

You get it if you have a registers and you do not reset them all.Thus to solve it add "next_state" to your reset part.

The older versions of Xilinx had a better warning message which just said that not all values where reset.

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The "next_state" behavior not specified in the "if (rst)" clause will do this. The sad part is that most simulation software will miss it, and some synthesis software (Quartus) will actually create a bogus circuit with unknown behavior...albeit with a warning.

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