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I'm designing a 4-layer pcb which consists of a GSM module, GPS module, a microcontroller (SAM4S) and a proper dc to dc buck converter.

The traces of the antennas are extremely short, fewer than 5mm long.

And the highest speed of signals is the SPI which I chose for external nor flash and/or a micro sdcard communication.

There are also few analog signals for monitoring very low frequencies (100 Hz in worst case).

I was thinking if it's a good idea to fill every unused space with ground plane stitching with vias (as if it's manufactured in cnc). I will not let any dead copper though.

Will this cause any problem in signal integrity?

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Don't do that, unless you know exactly what for. Creating unexpected capacitance is always a bad idea, as all kinds of AC stuff (mainly from switching devices, but not only) will travel the most unexpected ways.

Actually what you should do is to channel ac stuff exactly the way you want.

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  • \$\begingroup\$ I thought that ground was good practice, in general \$\endgroup\$ – MrBit Mar 16 '18 at 20:40
  • \$\begingroup\$ In some cases it is. If you have to cover something, if you need predictable z0. but not just pour copper and hope everything will be fine. \$\endgroup\$ – Gregory Kornblum Mar 16 '18 at 20:58
  • \$\begingroup\$ You can have predictable Z0 with ground poured, you just have to be extra careful about it. \$\endgroup\$ – Mike Mar 16 '18 at 21:02
  • \$\begingroup\$ Not just copper, but copper connected to ground with vias. \$\endgroup\$ – MrBit Mar 16 '18 at 21:04
  • \$\begingroup\$ That's what i said.. But when you don't need it- it's better not to pour ground. Because then everything below it will be capacitively coupled \$\endgroup\$ – Gregory Kornblum Mar 16 '18 at 21:05
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Most of the datasheets I saw had a recommendation, how to use the ground planes around the RF IC.

  • most of the chip/pcb antenna designs recommended no filling around the RF lines, similar to this one. Possible reasons: reduce parasitics, field-shaping, etc. Notice the stitching vias at the edge of the polygons. image source

enter image description here

  • I saw some designs with external antennas, that used filling around the RF line. Here you have to take care of the characteristic impedance of your line. If your RF line is a microstrip on the surface layer, then your refence is usually one of the internal layers. Thus you have to take care, that the filling on the outer layer is coupled much less to your signal, than the internal layers. The recommendations I've read mention a clearance around 3-4x the distance to the reference plane. image source

enter image description here

So my recommendation is:

  • check your datasheet recommendation or app. notes of the supplier
  • if there is nothing regarding this, I would leave the area around the antenna empty (no components, no copper, nothing at all), but I would separate the non-rf part with a filling + stitching vias, in order to make wave propagation inside the pcb impossible + reduce EM emission of the DC/DC

PS: regarding digital signals - it is not the SPI frequency that matters regarding signal integrity, but the rise and fall times of those signals. Rule of thumb: if your track is longer than 1/10-th of the way the signal travels during the rise/fall time, you might get reflection issues.

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