What can cause rise times to be slewed from an fpga to an enet Phy? Can it be trace capacitance?

This is a high density 14 layer board . Traces route from fpga to ribbon connector, along a short ribbon then along a second pcb up an Ethernet phy running at Gb enet using rgmii.

Using matching resistors driving side of the ribbon. 10bt and 100 bt work with some packet loss but Gb does not work . the rise times refardless of fpga settings the rise and fall times are slewed . So much do the sample and hold times for Gb enet can’t be met.

I have redesigned ribbon rather than all data to be gnd sig gnd sig gnd sig etc etc. Taking ribbon off or testing board with hard connections I still have slow rise times.

My gnd floods are 0.1mm or less from all enet signal lines and vias both sides. Could this add capacitance? Maybe vias? After solving this problem how do I si simulate the ribbon? Thanks.

  • \$\begingroup\$ Can you post a schematic, including the power delivery network? \$\endgroup\$ – Lior Bilia Mar 17 '18 at 0:42
  • \$\begingroup\$ Hard to do as it’s big but I can try and collate associated info. Why would the power delivery network affect it? The board is pads and vias, gnd , sig sig , vcc gnd, sig sig vcc gnd, sig sig Gnd, pads vias. \$\endgroup\$ – R B Mar 17 '18 at 9:03
  • \$\begingroup\$ Vcc has split planes or islands in Paralell with unbroken gnd planes. The enet schematic matches the dev schematic. Power supplies have plenty of spare current and Xilinx recommendation for decoupling is used as a min. Slewed lines are on arm core output from soc. \$\endgroup\$ – R B Mar 17 '18 at 9:05
  • \$\begingroup\$ Tracks are 40/50 ohms travel length matched to fpc connector. Gnd fill either side of all digital lines to 0.1mm or less. Vcc of Gnd plane above and below. 0.13mm copper filled laser vias used. Maybe via capacitance? Does this help got now as it’s the weekend. \$\endgroup\$ – R B Mar 17 '18 at 9:08
  • \$\begingroup\$ Some PHY chips have config register which allow to slightly vary the rise/fall times and clock/data skew. Also, depending on your FPGA, there may be a constraint to control the slew rate on output signals (for Xilinx the default slew rate is SLOW). \$\endgroup\$ – damage Mar 17 '18 at 14:49

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