What can cause rise times to be slewed from an fpga to an enet Phy? Can it be trace capacitance?
This is a high density 14 layer board . Traces route from fpga to ribbon connector, along a short ribbon then along a second pcb up an Ethernet phy running at Gb enet using rgmii.
Using matching resistors driving side of the ribbon. 10bt and 100 bt work with some packet loss but Gb does not work . the rise times refardless of fpga settings the rise and fall times are slewed . So much do the sample and hold times for Gb enet can’t be met.
I have redesigned ribbon rather than all data to be gnd sig gnd sig gnd sig etc etc. Taking ribbon off or testing board with hard connections I still have slow rise times.
My gnd floods are 0.1mm or less from all enet signal lines and vias both sides. Could this add capacitance? Maybe vias? After solving this problem how do I si simulate the ribbon? Thanks.