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I'm stuck with a sampling issue. I'm trying to sample a serial data line coming from a sensor. Basically, I send clk (max. 5Mhz) from the FPGA to the sensor, and then I receive the data bits from the sensor (1 bit per clock cycle).

I have written (in Verilog) a module to send a 5Mhz clk to the sensor, but I don't know how to sample a 5Mhz serial data line with a 50Mhz FPGA.

Any ideas?

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  • \$\begingroup\$ What kind of FPGA? Different ones have different input capabilities. \$\endgroup\$
    – crj11
    Mar 17 '18 at 0:48
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One simple way is to create a clock enable signal, which pulses high once every 10 clock cycles (of your 50 MHz system clock).

Register your incoming serial data as an input to a DFF, clocked with your system clock, and clock-enabled with the signal created above.

This keeps your registers clocked properly, and prevents cross-domain clocking issues.

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