I'm stuck with a sampling issue. I'm trying to sample a serial data line coming from a sensor. Basically, I send clk (max. 5Mhz) from the FPGA to the sensor, and then I receive the data bits from the sensor (1 bit per clock cycle).
I have written (in Verilog) a module to send a 5Mhz clk to the sensor, but I don't know how to sample a 5Mhz serial data line with a 50Mhz FPGA.