A priority interrupt controller has certain basic functionality that virtually all of this type share (as noted, certain specifics vary by device).
An example of one type might be useful.
Let's say I have a priority controller with 3 levels, A, B and C and that the priority order is A highest, B next, C lowest and each has been assigned to a particular event (timers perhaps, maybe a pin state change)
What could conceivably happen is this:
Interrupt C occurs; as there is currently no other interrupt pending, the interrupt vector is taken.
Before the interrupt handler for C completes, interrupt A occurs; the interrupt handler for C is suspended and the interrupt vector for interrupt A is taken (because interrupt A has a higher priority).
Prior to the interrupt handler for A finishing, interrupt B occurs; the interrupt handler for interrupt A continues (because B has a lower priority) until it completes and execution returns to the interrupt C handler (because that is where the processor was when interrupt A occurred).
The interrupt vector is immediately taken for interrupt B (because it has a higher priority than interrupt C) and completes the handler.
Execution now returns to interrupt C handler which can now complete (assuming neither of the other two interrupts happen in that time).
This is but one type of controller architecture, but it might give you the flavour of what these things do.