I'm designing a board with a fairly high frequency chip. It uses a 2.5GHz clock and can drive outputs of +-30mA total with edge rates in the 300ps range.
There is a reference design using this which has it bypassed with a 47nF IDC capacitor about 3mm away from the power pins and opposite side of the board (and through 4 vias in parallel). Back of the envelope, the loop inductance is around 1000pH. Considering the frequency, that inductance seems rather high (and the use of an IDC capacitor totally pointless). There are also a couple of larger capacitors (200nF total) which are even further out (let's say 6mm and >2000pH).
I've done some simulations and it seems that there almost has to be a fairly sizeable capacitance either on the chip itself or in the package, for the chip to function at all. If I assume the supply voltage as seen on-chip oscillates by around 10mV, there is must be over 1nF bypass capacitance on-chip. Is that realistic?
Here is my model in Spice (ADIsimPE):
If that model is close to accurate, then changing either the value of the external bypass capacitor or the inductance of the loop between it and the chip (let's say within an order of magnitude up or down) has little effect on the size of the supply peak-to-peak swing as seen on-chip. It does however affect the frequency (or rather multiple frequencies) of the swings. It seems that despite the high frequency, because the chip is internally bypassed, it is probably rather insensitive to the quality of the external bypassing.
Is there a way to measure the effective on-chip capacitance?