From point of view of a synthesiser, is there any difference between:
Signal offset: std_logic_vector ( 3 downto 0) := "0100";
Constant offset: std_logic_vector ( 3 downto 0) := "0100";
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Nope. However "constant" cannot be assigned any value. Its value can never change during simulation. Otherwise its just like "signal" itself. It is just used to improve maintainability, readability and clarity in the code to the user. One use of constant is:
constant const: integer := 7; signal a: std_logic_vector(const downto 0); signal b: std_logic_vector(const downto 0); signal c: std_logic_vector(const+1 downto 0);
In future, if you want to change the bus width, you just need to change the initialising value of const.
Note that - As @damage pointed out, we usually do all initialisation by asserting reset signal in the beginning. However I have seen that most FPGA synthesisers synthesise the initialised value.
No, for almost all synthesis tools there will be no difference.
However, people with a background in ASIC design will discourage the use of initial values for signals and recommend the use of a resest signal to set the initial value. This is because for ASICs there is no configuration phase as for FPGAs and registers will usually be in an unknown state after power-on.
For FPGAs some vendors will recommend the use of initial values instead of resets whenever possible, since this can result in lower resource utilization. This is because during the configuration phase of SRAM-based FPGAs, when the bitstream is loaded to the FPGA, each register can be set to an initial value.
For simulation it will make no difference too.