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After adding the counter to my VHDL code am getting the following error: Error (10316): VHDL error at ASM.vhd(31): character ''0'' used but not declared for type "std_logic_vector" Thank you

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ASM is
port(clk, rst, A, B,DOOR: in std_logic;
    Z:buffer std_logic_vector(1 downto 0));
end ASM;

architecture asm1 of ASM is

type t_state is(T0,T1,T2,T3,T4,T5);
signal count:std_logic_vector(2 downto 0);
signal next_state:t_state;
signal current_state:t_state:=T0;
signal tempz:std_logic_vector(1 downto 0):= (others => '0');

begin
clock:process(clk,rst)
begin
    if(rst='1')then
        current_state<=T0;
    elsif(clk'event and clk='1') then
        current_state<=next_state;
    end if;

end process;

next_state_decoder:process(current_state,A,B,DOOR,count)
begin
count<='0';
case current_state is
    when T0=> if(A='0')and(B='0') then 
                   count<= count+'1';
                    if(counter_out = 5) then                    
                        next_state<=T1;
                    end if;
                else
                    next_state<=T0;
                end if;

    when T1=>if(A='1')and(B='0')then
                    count<= count+'1';
                    if(counter_out =  5) then
                        next_state<=T2;
                    end if;
                else
                    next_state<=T0;
                end if; 

    when T2=>if(A='1')and(B='1')then
                    count<= count+'1';
                    if(counter_out = 5 ) then
                        next_state<=T3;
                    end if; 
                else
                    next_state<=T4; 
                end if;

    when T3=> if(DOOR='0')then
                 next_state<=T0;
                 else 
                 next_state<=T3;
                 end if;

    when T4=>if(A='0')and(B='1')then 
                    count<= count+'1';
                    if(counter_out = 5 ) then
                        next_state<=T5;
                    end if;
                else
                next_state<=T4;
                end if;

    when T5=> if(DOOR='1')then
                next_state<=T0;
                else
                next_state<=T4;
                end if;

    when others=> NULL;

  end case;
end process;

output_decoder:process(clk,A,B,current_state,DOOR)
begin
if(clk'event and clk='1') then
case(current_state) is
    when T0=>tempz<="00";

    when T1=>tempz<="00";

    when T2=>tempz<="00";

    when T3=>tempz<="10";

    when T4=>tempz<="00";

    when T5=>tempz<="11";

    when others=> null;

end case;
end if;
end process;
Z<=tempz;
end asm1;
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  • \$\begingroup\$ You are assigning a single bit to a three bit vector. \$\endgroup\$ – Brian Drummond Mar 17 '18 at 15:00
  • \$\begingroup\$ if you write '1' or '0' it means single bit 1 or 0, not number 1 or 0. \$\endgroup\$ – Staszek Mar 17 '18 at 15:07
  • \$\begingroup\$ Try: count <= count + "001"; \$\endgroup\$ – TonyM Mar 17 '18 at 21:56
  • \$\begingroup\$ Line 31 appears to be count<='0'; where the type on the left hand side of the assignment is std_logic_vector and the type of the expression on the right hand is a character literal and not a bit string literal. Use count<=(others => '0'); where the aggregate (an array composite value) get's it's type and subtype from the left hand side (from context). \$\endgroup\$ – user8352 Mar 17 '18 at 22:15
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VHDL is strongly typed language.

  • count is a 3-bit vector. You should assign it as "000", not '0'

  • adding should be like count <= count + "001"

  • counter_out has not been declared.

  • in your second process, count will never increment after "001". As it is always assigned "000" in the beginning of the process.

  • your if blocks dont have else block in the second process. Also, on reset initialise all signals to a known initial state. And make sure that all signals are assigned some value in all possible input combinations. It will avoid inferring latches during synthesis.

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