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The design is basically a copy from a reference design. I used a few different tools to calculate the trace impedance with different results. While the manufacturer uses Si9000, the result does not match with what the other tools get.

The questions are:

  • Which of the results below is the accurate?
  • If the reference design is not that accurate in impedance control, how to evaluate the effect of the mismatch on the actual PCB it produces?

The questions are mostly on the inner layer differential impedance item [4] below.

Details:

In the list below, [1] is the reference design stackup information; [2] and [3] are the processes to get the result close enough to the reference design target so as to know the tool is valid; and [4] is the calculation in question because it is either 5% higher than the target or 10% lower.

  • [1] The reference stackup information is read from an original .brd file by an "Allegro Free Physical Viewer 17.2". The screenshot is as shown in the picture q1-pro-pcb.png q1-pro-pcb.png . As also noted in the picture, the subsequent calculations are on the: [2] top-layer single-end impedance; [3] top-layer differential impedance; [4] inner-layer differential impedance.

  • [2] Calculate the top layer signal end impedance: Two tools are giving Zo=48 and Zo=47. Assuming both are accurate enough.

    • [2.1] Using the "Saturn PCB Toolkit V7.04", set W=3.5, H=2, F=500MHz, T=1.05, Er=4.5, the result is Zo=48 Ohms. This is close enough to the 50 Ohms target. It gives an Effective Er=3.12.
    • [2.2] Using the online Montaro Impedance Calculator, choose Microstrip Zo. Set w=3.5, t=1.05, h=2, Er=3.12, the result is Zo=46.3. Change to t=1.0, the result is Zo=46.9.
  • [3] Calculate the top layer differential impedance:

    • [3.1] Using Montaro, choose Microstrip Zdiff. Set w=3, d=6.5, t=1, h=2, er=3.12. The result is Zd=100.6.
  • [4] Calculate the inner layer differential impedance:

    • [4.1] Using Montaro, choose Asymmetric Zo. Set w=3, t=1, h=3, h1=10, er=3.12, the result is Zo=57.143. Then choose Zdiff from Zo, set Zo=57.143, d=7, h=14, the result is Zd=104.984.
    • [4.2] Using the "Polar Si9000 PCB Transmission Line Field Solver v7.1.0", set H1=10, H2=4, Er1=Er2=4.5, S1=7, W1=W2=3, T1=1, the result Zdiff=90.02. See the picture q42-polar-si9000.png enter image description here .
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All results are accurate to the assumptions and parameters you enter in. As I see, you took a liberty to use nearly arbitrary values for dielectric constant, from 2.45, 3.11-12, to 4.5. And 5% or 10 % makes no difference and usually is impossible to meet from first calculations, if ever.

What you need to do is to get your preferred PCB manufacturer, and request their preferable stack-up, copper thickness, prepeg thickness, and dielectric constant. With their guaranteed manufacturing tolerances. Then pick some reasonable trace geometry. Don't forget to notify the house about "impedance controlled design", a good house will correct the width of your traces for overetch, so the final width will be as specified. And include several variants of test coupons, with access points to a VNA. If you really believe that you need traces with better than 10% match (or you have some paranoid manager), you test your coupons for impedance, and if it doesn't meet your expectations, you cut the board and verify trace/stack dimensions, and either talk back to manufacturing house, or make necessary adjustments. And spin another board, until you get your impedance right.

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  • \$\begingroup\$ 3.11 is a typo on my side, changed to 3.12 the result changes from 100.8 to 100.6. Where is 2.45? I use 3.12 because at [2.1] er=4.5 turns out an "effective er=3.12". Thus I think instead of 4.5 I should use 3.12 for it on mantaro site at [4.1]. Is this something right or wrong? At [4.2] if I change 4.5 to 3.12, the result would be about 105 or 5% higher than the standard 100 target. Thanks for many other insights. \$\endgroup\$ – minghua Mar 18 '18 at 3:48

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