# Ungrouping synthesized modules in Synopsys Design Compiler for better synthesis results

I have a large multi-input multi-output design where each primary output is written in terms of primary inputs. Because the design is so large, DC is unable to synthesize the circuit. A straightforward solution is to synthesize each output individually and later, synthesize the bigger design by instantiating these smaller modules. However, I think there is a lot of room for optimization because all output functions share the exact same inputs.

Does ungrouping different designs optimize mostly around the boundaries or will optimize the whole design regardless of whether each smaller module has been synthesized before or not? If it optimizes the design as a whole, is there an advantage to synthesizing smaller modules first?

In other words, I like to use a divide and conquer method that synthesizes smaller modules first, but takes advantage of the fact that small modules share the same inputs and optimize around boundaries. Is there a set of DC commands that can achieve this?

Does ungrouping different designs optimize mostly around the boundaries or will optimize the whole design regardless of whether each smaller module has been synthesized before or not?

There is no difference between an RTL design and a post-synthesis netlist. Design Compiler tries to optimize both of them as long as the constraints (e.g. dont_touch) and synthesis options (ungrouping, boundary optimization etc.) permit. DC also has an option for the optimization strategy, I'll show below.

If it optimizes the design as a whole, is there an advantage to synthesizing smaller modules first?

It's hard to predict. Different options and optimization strategies don't give the same results in all cases. I have experienced that sometimes ungrouping a whole project gives worse results (timing, area etc.). The best thing to do is to try a few sets of options and to continue with the best resulting one.

Is there a set of DC commands that can achieve this?

I haven't tried myself, but there are two strategies to optimize a design.

1. Each output in my_module is optimized individually.

set_flatten -design <my_module> -minimize single_output

2. The design is optimized as a whole.

set_flatten -design <my_module> -minimize multiple_output

• Thanks for the great answer. Should I run compile normally (without any additional arguments) after setting set_flatten? – Mahdi Mar 20 '18 at 22:24
• @Mahdi Yes, my_module should be flattened regardless of the global settings. I think there is no need to change any setting alongside compile or compile_ultra command. – ahmedus Mar 21 '18 at 11:19