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These days you can't read anything about electronics without hearing about the dire consequences of omitting ESD protection from your designs.

It seems this wasn't always the case. If you look at most older designs (late 90s and earlier), you hardly ever see ESD protection components on I/O ports - even when CMOS ICs are involved. Why is this?

One might assume that modern ICs are more vulnerable than older processes. I don't think there's much truth to that though. Looking at the datasheet for a typical 74HC gate, they specify a maximum HBM of 2kV. This is the same as a modern MCU or FPGA.

I could understand designs using 74LS gates omitting protection, but I also see lack of protection when 74HC or CMOS LSIs are used in older designs. And having looked at more recent datasheets for 74LS parts, even those are specified only up to 2kV HBM.

Is it just that we have a better awareness of ESD now? Or could it be that you can actually still get away without ESD protection just as they did in the 90s? Is there a minimum level of ESD robustness required by law for consumer products, that wasn't enforced in the past?

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    \$\begingroup\$ There is some historical perspective in this article. The author mentions that the ESD test standards were becoming more stringent over time. \$\endgroup\$ Mar 19, 2018 at 2:33
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    \$\begingroup\$ The RCA COS MOS data book published in 1979 devotes a chapter to handling and ESD protection. Link: archive.org/details/RcaCosmosIntegratedCircuitsManual \$\endgroup\$
    – AlmostDone
    Mar 19, 2018 at 3:07
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    \$\begingroup\$ maximum HBM of 2kV .... you walk across a carpet, and you will have 30kV+ available to zap stuff \$\endgroup\$
    – jsotola
    Mar 19, 2018 at 3:43
  • \$\begingroup\$ One reason it may have become more critical is that the manufacturing spacing is so much smaller now - the early chips were so much bigger and the track or pin spacing had more insulation between them... \$\endgroup\$
    – Solar Mike
    Mar 19, 2018 at 8:13

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I can only speak from my personal view...

In the 80's, there was a thorough awareness of the need for ESD protection and handling precautions. My then-employer modernised its factory in 1987, taking ESD precautions from only in the electronics assembly areas to every assembly area. The consensus was that we were very late in the day to do so. The understanding of ESD that I see is no more stringent or widespread than then.

What has changed considerably since then are the costs of electronic components and of PCB design, manufacture and assembly. I've seen these get dramatically cheaper.

So the costs of adding extra parts, such as transorbs, TVS or input filters are much cheaper. Back then, in the commercial industry I worked in, these protection parts would be an unacceptable increase in cost. It's not just the component cost, its the price of the inventory, assembly and testing that goes with having those parts there.

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  • \$\begingroup\$ This is useful to know! Would it be true to say that unprotected equipment from the 80s and 90s (that used CMOS) is just as vulnerable as unprotected equipment today? What's interesting is that I've never seen or heard of an I/O port failure on older equipment. This suggests either older CMOS ICs really were more robust (despite having the same HBM rating) or ESD protection on I/O ports is still not always necessary even today. One thing I do see in older American equipment is ferrite beads on I/O. This may take the edge off the ESD. But EU equipment hardly ever had I/O filters. \$\endgroup\$
    – Foxie
    Mar 19, 2018 at 17:12
  • \$\begingroup\$ @Foxie, can't give you the general case but my experience was to have very few parts fail then and now through ESD and I'm pretty cavalier (careless) about static protection. But I do design boards to be ESD resistant for general handling as far as I can with budget available. I put leakage resistors across GND and logic/FET outputs going to connectors so ESD can bypass the part, which has always worked well for me, or using proper protected interface ICs. My first job was designing for office equipment so user ESD protection and EMC were paramount, along with cost and reliability. Taught me! \$\endgroup\$
    – TonyM
    Mar 19, 2018 at 17:39
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As long as some junctions are tied to input pins, and not just MOS-gates, the older CMOS seems tolerant to modest charges such as sliding into ESD_proof mylar envelopes.

The outputs of CMOS are by definition "junctions", because FET drains are tied to the output pins, to aggressively pull up or pull down. These drains are not optimized for ESD energy processing.

For ESD survival, the charge needs to be taken DEEP into the bulk silicon where lots of mass is available to absorb the ESD energy. Fast CMOS PMOS and NMOS are designed for speed, and are built on the surface.

Thus modern ESD structures may use special implants, deep implants, to include mass for energy absorption.

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  • \$\begingroup\$ Thus modern ESD structures may use special implants, deep implants, to include mass for energy absorption. I have yet to see an actual CMOS process having that. In the real world ESD structures are simply large so that they are able to handle the current without dropping too much voltage so that the circuits don't suffer too much over voltage. \$\endgroup\$ Mar 19, 2018 at 6:56
  • \$\begingroup\$ Wouldn't drains still be vulnerable to ESD damage, by exposing the gate oxide to a high voltage? The commonly seen simplified diagram of a MOSFET doesn't make this obvious, but I found one more accurate diagram which shows the drain is directly in contact with the gate oxide. The only way the gate oxide could avoid damage is if the body diode breaks down first. Can this be relied upon? \$\endgroup\$
    – Foxie
    Mar 19, 2018 at 14:32
  • \$\begingroup\$ @ Foxie Not being an ESD-structure design/layout jock, I can only share what I recall from prior IC work. \$\endgroup\$ Mar 20, 2018 at 4:06
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Any manufacturing plant worth a nickel pays a great deal of attention to ESD-or else suffer losses while a board is still in process.

  1. The 74cxx and 74HCxx have some diode protection, but the CD4000 and outdated 74Fxx series has little to none. Walk on a carpet and touch a lead while it is on a table top and consider it gone. It was easy to test for a blown CMOS part, as I would get a positive voltage reading out of an input pin.

  2. Along with IC's we had trouble with the newer generation of LED's blowing from the stock room not handling them with anti-static bags. As part of engineering I had warned them, but it took blown parts and a verbal assault by the company VP to get things in order.

So there is much better awareness across the board in terms of ESD, mostly a stockroom and assembly issue.

You can no longer 'get away' without grounding wrist and ankle straps, and a grounded solder iron.

ISO does pay attention to this issue, but only in terms of how a company manages internal ESD issues. Do they have procedures in place and do they follow them when an ESD incident occurs and take corrective action?

There is no government issued ESD regulations unless you care to follow military or NASA procedures, but none the less ISO will force a manufacturing plant to work out and implement ESD procedures.

No, you can't pay the ISO person to look the other way. They make plenty of money and are often escorted by a senior employee or a trainee.

Once ESD protection permeates a manufacturing plant, an ESD based failure can usually be traced back to someone new or who has poor English skills, so it becomes a re-training issue, or a documentation issue. ISO looks into ALL your documents to find a root document, at the base of the document tree.

This is a link to a 3M document on ESD and the fine details: LINK

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